APA (7th ed.) Citation

Liang, X., Canal, R., & Wei, G. (2008). Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability. IEEE Micro, 28(1), 60. https://doi.org/10.1109/MM.2008.12

Chicago Style (17th ed.) Citation

Liang, Xiaoyao, Ramon Canal, and Gu-Yeon Wei. "Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability." IEEE Micro 28, no. 1 (2008): 60. https://doi.org/10.1109/MM.2008.12.

MLA (9th ed.) Citation

Liang, Xiaoyao, et al. "Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability." IEEE Micro, vol. 28, no. 1, 2008, p. 60, https://doi.org/10.1109/MM.2008.12.