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Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.

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Bibliographic Details
Title: Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.
Authors: Liang, Xiaoyao, Canal, Ramon, Wei, Gu-Yeon
Source: IEEE Micro; January/February 2008, Vol. 28 Issue 1, p60-68, 9p
Database: Applied Science & Technology Source
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  Availability: 0
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DbLabel: Applied Science & Technology Source
An: 501532052
AccessLevel: 2
PubType: Academic Journal
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        Value: 10.1109/MM.2008.12
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        Text: English
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        PageCount: 9
        StartPage: 60
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      – TitleFull: Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.
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            NameFull: Liang, Xiaoyao
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            NameFull: Canal, Ramon
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              Text: January/February 2008
              Type: published
              Y: 2008
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