Andalam, S., Girault, A., Sinha, R., Roop, P., & Reineke, J. (2013). Precise Timing Analysis for Direct-Mapped Caches. DAC: Annual ACM/IEEE Design Automation Conference, 1.
Chicago Style (17th ed.) CitationAndalam, Sidharta, Alain Girault, Roopak Sinha, Partha Roop, and Jan Reineke. "Precise Timing Analysis for Direct-Mapped Caches." DAC: Annual ACM/IEEE Design Automation Conference 2013: 1.
MLA (9th ed.) CitationAndalam, Sidharta, et al. "Precise Timing Analysis for Direct-Mapped Caches." DAC: Annual ACM/IEEE Design Automation Conference, 2013, p. 1.
Warning: These citations may not always be 100% accurate.