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[formula omitted]RVFormal: Formal verification of RISC-V processor Chisel designs.

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Title: [formula omitted]RVFormal: Formal verification of RISC-V processor Chisel designs.
Authors: Shen, Shidong1,2 (AUTHOR) shensd@ios.ac.cn, Chen, Shijie1,2 (AUTHOR) chensj@ios.ac.cn, Liu, Yicheng1,2 (AUTHOR) liuyc@ios.ac.cn, Zhang, Lijun1,2 (AUTHOR) zhanglj@ios.ac.cn, Song, Fu1,2,3 (AUTHOR) songfu@ios.ac.cn, Wu, Zhilin1,2 (AUTHOR) wuzl@ios.ac.cn
Source: Journal of Systems Architecture. Jun2026, Vol. 175, pN.PAG-N.PAG. 1p.
Database: Business Source Ultimate
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Header DbId: bsu
DbLabel: Business Source Ultimate
An: 193396275
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
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Items – Name: Title
  Label: Title
  Group: Ti
  Data: [formula omitted]RVFormal: Formal verification of RISC-V processor Chisel designs.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Shen%2C+Shidong%22">Shen, Shidong</searchLink><relatesTo>1,2</relatesTo> (AUTHOR)<i> shensd@ios.ac.cn</i><br /><searchLink fieldCode="AR" term="%22Chen%2C+Shijie%22">Chen, Shijie</searchLink><relatesTo>1,2</relatesTo> (AUTHOR)<i> chensj@ios.ac.cn</i><br /><searchLink fieldCode="AR" term="%22Liu%2C+Yicheng%22">Liu, Yicheng</searchLink><relatesTo>1,2</relatesTo> (AUTHOR)<i> liuyc@ios.ac.cn</i><br /><searchLink fieldCode="AR" term="%22Zhang%2C+Lijun%22">Zhang, Lijun</searchLink><relatesTo>1,2</relatesTo> (AUTHOR)<i> zhanglj@ios.ac.cn</i><br /><searchLink fieldCode="AR" term="%22Song%2C+Fu%22">Song, Fu</searchLink><relatesTo>1,2,3</relatesTo> (AUTHOR)<i> songfu@ios.ac.cn</i><br /><searchLink fieldCode="AR" term="%22Wu%2C+Zhilin%22">Wu, Zhilin</searchLink><relatesTo>1,2</relatesTo> (AUTHOR)<i> wuzl@ios.ac.cn</i>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Journal+of+Systems+Architecture%22">Journal of Systems Architecture</searchLink>. Jun2026, Vol. 175, pN.PAG-N.PAG. 1p.
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=bsu&AN=193396275
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1016/j.sysarc.2026.103761
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 1
        StartPage: N.PAG
    Titles:
      – TitleFull: [formula omitted]RVFormal: Formal verification of RISC-V processor Chisel designs.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Shen, Shidong
      – PersonEntity:
          Name:
            NameFull: Chen, Shijie
      – PersonEntity:
          Name:
            NameFull: Liu, Yicheng
      – PersonEntity:
          Name:
            NameFull: Zhang, Lijun
      – PersonEntity:
          Name:
            NameFull: Song, Fu
      – PersonEntity:
          Name:
            NameFull: Wu, Zhilin
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 06
              Text: Jun2026
              Type: published
              Y: 2026
          Identifiers:
            – Type: issn-print
              Value: 13837621
          Numbering:
            – Type: volume
              Value: 175
          Titles:
            – TitleFull: Journal of Systems Architecture
              Type: main
ResultId 1