Ho, K., Chan, C., Choy, C., & Pun, K. (2003). Reversed Nested Miller Compensation With Voltage Buffer and Nulling Resistor. IEEE Journal of Solid-State Circuits, 38(10), 1735. https://doi.org/10.1109/JSSC.2003.817598
Chicago Style (17th ed.) CitationHo, Kin-Pui, Cheong-Fat Chan, Chiu-Sing Choy, and Kong-Pang Pun. "Reversed Nested Miller Compensation With Voltage Buffer and Nulling Resistor." IEEE Journal of Solid-State Circuits 38, no. 10 (2003): 1735. https://doi.org/10.1109/JSSC.2003.817598.
MLA (9th ed.) CitationHo, Kin-Pui, et al. "Reversed Nested Miller Compensation With Voltage Buffer and Nulling Resistor." IEEE Journal of Solid-State Circuits, vol. 38, no. 10, 2003, p. 1735, https://doi.org/10.1109/JSSC.2003.817598.
Warning: These citations may not always be 100% accurate.