Reversed Nested Miller Compensation With Voltage Buffer and Nulling Resistor.
Saved in:
| Title: | Reversed Nested Miller Compensation With Voltage Buffer and Nulling Resistor. |
|---|---|
| Authors: | Kin-Pui Ho1 cfchan@ee.cuhk.edu.hk, Cheong-Fat Chan1, Chiu-Sing Choy1, Kong-Pang Pun1 |
| Source: | IEEE Journal of Solid-State Circuits. Oct2003, Vol. 38 Issue 10, p1735-1738. 4p. 1 Black and White Photograph, 3 Diagrams, 4 Charts. |
| Subjects: | Electronic amplifiers, Electric resistors |
| Abstract: | This paper presents a new reversed nested Miller compensation technique for multistage operational amplifier (opamp) design. The new compensation technique inverts the sign of the right half complex plane zero and shifts the frequency of the complex conjugate poles to a higher frequency. Simulation results indicate that the gain-bandwidth product and settling time are improved by factors of two and three, respectively, without degrading stability and power consumption. To verify the proposed technique, a three-stage opamp is fabricated with 0.6-µm CMOS technology. The measured results of the test circuit agree with the results that are obtained from theoretical analysis and circuit simulation. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
Be the first to leave a comment!
