Evaluating the use of adder compressors for power-efficient HEVC interpolation filter architecture.
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| Title: | Evaluating the use of adder compressors for power-efficient HEVC interpolation filter architecture. |
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| Authors: | Diniz, Cláudio1 claudio.diniz@ucpel.edu.br, Fonseca, Mateus1, Costa, Eduardo1, Bampi, Sergio1 |
| Source: | Analog Integrated Circuits & Signal Processing. Oct2016, Vol. 89 Issue 1, p111-120. 10p. |
| Subjects: | Adders (Digital electronics), Compressor efficiency, Electric filters, Video coding, Interpolation algorithms, Very large scale circuit integration, Motion compensation (Signal processing), Motion estimation (Signal processing) |
| Abstract: | The recent High Efficient Video Coding (HEVC) standard introduces a new and complex interpolation filter for fractional-pixel motion estimation and motion compensation. Recent works propose hardware architectures to accelerate the interpolation filter, employing interpolation datapaths with many adders in parallel. Adder compressors are power-efficient operators, that are applied when intermediate additions are not required, which is the case for interpolation filters. This work evaluates the use of different 7-2 and 8-2 adder compressors structures in the interpolation datapaths of a recent HEVC interpolation filter architecture targeting power efficiency. Results show that 7-2 adder compressor (composed with basic 4-2 and 3-2 adder compressors) and 8-2 adder compressor (composed with basic 4-2 adder compressors) reduce power delay product by 16 and 19 %, respectively, compared with adders generated by the synthesis tool. These adder compressors achieved the best results in terms of PDP compared with many classical adders. The full interpolation filter architecture using the best adder compressors dissipates 9967.1 µW of power and consumes 28.21 pJ of energy per operation. [ABSTRACT FROM AUTHOR] |
| Copyright of Analog Integrated Circuits & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 118029675 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Evaluating the use of adder compressors for power-efficient HEVC interpolation filter architecture. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Diniz%2C+Cláudio%22">Diniz, Cláudio</searchLink><relatesTo>1</relatesTo><i> claudio.diniz@ucpel.edu.br</i><br /><searchLink fieldCode="AR" term="%22Fonseca%2C+Mateus%22">Fonseca, Mateus</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Costa%2C+Eduardo%22">Costa, Eduardo</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Bampi%2C+Sergio%22">Bampi, Sergio</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Analog+Integrated+Circuits+%26+Signal+Processing%22">Analog Integrated Circuits & Signal Processing</searchLink>. Oct2016, Vol. 89 Issue 1, p111-120. 10p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Adders+%28Digital+electronics%29%22">Adders (Digital electronics)</searchLink><br /><searchLink fieldCode="DE" term="%22Compressor+efficiency%22">Compressor efficiency</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+filters%22">Electric filters</searchLink><br /><searchLink fieldCode="DE" term="%22Video+coding%22">Video coding</searchLink><br /><searchLink fieldCode="DE" term="%22Interpolation+algorithms%22">Interpolation algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Very+large+scale+circuit+integration%22">Very large scale circuit integration</searchLink><br /><searchLink fieldCode="DE" term="%22Motion+compensation+%28Signal+processing%29%22">Motion compensation (Signal processing)</searchLink><br /><searchLink fieldCode="DE" term="%22Motion+estimation+%28Signal+processing%29%22">Motion estimation (Signal processing)</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: The recent High Efficient Video Coding (HEVC) standard introduces a new and complex interpolation filter for fractional-pixel motion estimation and motion compensation. Recent works propose hardware architectures to accelerate the interpolation filter, employing interpolation datapaths with many adders in parallel. Adder compressors are power-efficient operators, that are applied when intermediate additions are not required, which is the case for interpolation filters. This work evaluates the use of different 7-2 and 8-2 adder compressors structures in the interpolation datapaths of a recent HEVC interpolation filter architecture targeting power efficiency. Results show that 7-2 adder compressor (composed with basic 4-2 and 3-2 adder compressors) and 8-2 adder compressor (composed with basic 4-2 adder compressors) reduce power delay product by 16 and 19 %, respectively, compared with adders generated by the synthesis tool. These adder compressors achieved the best results in terms of PDP compared with many classical adders. The full interpolation filter architecture using the best adder compressors dissipates 9967.1 µW of power and consumes 28.21 pJ of energy per operation. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Analog Integrated Circuits & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s10470-016-0765-6 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 10 StartPage: 111 Subjects: – SubjectFull: Adders (Digital electronics) Type: general – SubjectFull: Compressor efficiency Type: general – SubjectFull: Electric filters Type: general – SubjectFull: Video coding Type: general – SubjectFull: Interpolation algorithms Type: general – SubjectFull: Very large scale circuit integration Type: general – SubjectFull: Motion compensation (Signal processing) Type: general – SubjectFull: Motion estimation (Signal processing) Type: general Titles: – TitleFull: Evaluating the use of adder compressors for power-efficient HEVC interpolation filter architecture. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Diniz, Cláudio – PersonEntity: Name: NameFull: Fonseca, Mateus – PersonEntity: Name: NameFull: Costa, Eduardo – PersonEntity: Name: NameFull: Bampi, Sergio IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 10 Text: Oct2016 Type: published Y: 2016 Identifiers: – Type: issn-print Value: 09251030 Numbering: – Type: volume Value: 89 – Type: issue Value: 1 Titles: – TitleFull: Analog Integrated Circuits & Signal Processing Type: main |
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