Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors.
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| Title: | Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors. |
|---|---|
| Authors: | Grudnitsky, Artjom1, Bauer, Lars1, Henkel, Jorg1 |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Feb2017, Vol. 25 Issue 2, p594-607. 14p. |
| Subjects: | Adaptive computing systems, Run time systems (Computer science), Field programmable gate arrays |
| Abstract: | Reconfigurable processors with fine-grained runtime-reconfigurable fabrics are used to speed up applications from different domains. Such a reconfigurable fabric allows loading of application-specific accelerators, where multiple accelerators can be combined using a coarse-grained runtimereconfigurable μProgram to speed up complex computationally intensive kernels. To allow a large degree of adaptivity in the reconfigurable fabric, as it is required by, e.g., multitasking systems, the μProgram for a kernel should not be generated at compile time, as it would constrain the adaptivity of the system. To enable flexible and efficient use of the reconfigurable fabric, we propose the necessary algorithms for runtime: 1) accelerator placement (i.e., deciding where on the fabric an accelerator should be reconfigured at runtime); 2) μProgram generation; and 3) μProgram caching. Accelerator synthesis and implementation are done at compile time to reduce runtime overhead in generating accelerators. We evaluate the proposed algorithms using different application scenarios and demonstrate the proposed concepts on an field-programmable gate array-based prototype of a reconfigurable processor. In comparison with state-of-the-art reconfigurable processors that generate μPrograms at compile time, we obtain an average speedup of 1.29× (up to 1.84×). [ABSTRACT FROM PUBLISHER] |
| Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 127949071 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Grudnitsky%2C+Artjom%22">Grudnitsky, Artjom</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Bauer%2C+Lars%22">Bauer, Lars</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Henkel%2C+Jorg%22">Henkel, Jorg</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Very+Large+Scale+Integration+%28VLSI%29+Systems%22">IEEE Transactions on Very Large Scale Integration (VLSI) Systems</searchLink>. Feb2017, Vol. 25 Issue 2, p594-607. 14p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Adaptive+computing+systems%22">Adaptive computing systems</searchLink><br /><searchLink fieldCode="DE" term="%22Run+time+systems+%28Computer+science%29%22">Run time systems (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Reconfigurable processors with fine-grained runtime-reconfigurable fabrics are used to speed up applications from different domains. Such a reconfigurable fabric allows loading of application-specific accelerators, where multiple accelerators can be combined using a coarse-grained runtimereconfigurable μProgram to speed up complex computationally intensive kernels. To allow a large degree of adaptivity in the reconfigurable fabric, as it is required by, e.g., multitasking systems, the μProgram for a kernel should not be generated at compile time, as it would constrain the adaptivity of the system. To enable flexible and efficient use of the reconfigurable fabric, we propose the necessary algorithms for runtime: 1) accelerator placement (i.e., deciding where on the fabric an accelerator should be reconfigured at runtime); 2) μProgram generation; and 3) μProgram caching. Accelerator synthesis and implementation are done at compile time to reduce runtime overhead in generating accelerators. We evaluate the proposed algorithms using different application scenarios and demonstrate the proposed concepts on an field-programmable gate array-based prototype of a reconfigurable processor. In comparison with state-of-the-art reconfigurable processors that generate μPrograms at compile time, we obtain an average speedup of 1.29× (up to 1.84×). [ABSTRACT FROM PUBLISHER] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TVLSI.2016.2585603 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 14 StartPage: 594 Subjects: – SubjectFull: Adaptive computing systems Type: general – SubjectFull: Run time systems (Computer science) Type: general – SubjectFull: Field programmable gate arrays Type: general Titles: – TitleFull: Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Grudnitsky, Artjom – PersonEntity: Name: NameFull: Bauer, Lars – PersonEntity: Name: NameFull: Henkel, Jorg IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 02 Text: Feb2017 Type: published Y: 2017 Identifiers: – Type: issn-print Value: 10638210 Numbering: – Type: volume Value: 25 – Type: issue Value: 2 Titles: – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems Type: main |
| ResultId | 1 |
