Hierarchical multicore thread mapping via estimation of remote communication.
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| Title: | Hierarchical multicore thread mapping via estimation of remote communication. |
|---|---|
| Authors: | Khaleghzadeh, Hamidreza1 hamidreza.khaleghzadeh@ucdconnect.ie, Deldari, Hossein2 hdeldari@salman.ac.ir, Reddy, Ravi1 ravi.manumachu@ucd.ie, Lastovetsky, Alexey1 alexey.lastovetsky@ucd.ie |
| Source: | Journal of Supercomputing. Mar2018, Vol. 74 Issue 3, p1321-1340. 20p. |
| Subjects: | Multicore processors, Threads (Computer programs), Cache memory, Information sharing, Estimation theory |
| Abstract: | Affinity-aware thread mapping is a method to effectively exploit cache resources in multicore processors. We propose an affinity- and architecture-aware thread mapping technique which maximizes data reuse and minimizes remote communications and cache coherency costs of multi-threaded applications. It consists of three main components: Data Sharing Estimator, Affine Mapping Finder and Maximum Speedup Predictor. Data Sharing Estimator creates application-specific data dependency signatures used by Affine Mapping Finder to determine the appropriate thread mapping of application for a given architecture. To prevent excessive thread migration, Maximum Speedup Predictor estimates the speedup of the obtained mapping and ignores it if it causes no significant performance improvement. The proposed framework is evaluated using Phoenix benchmark suite on two different multicore architectures. The proposed thread mapping approach gives 25% improvement in performance compared to default Linux scheduler. We also elucidate that affinity-based thread mapping approaches, which only consider the number of shared blocks, are not appropriate enough to accurately estimate data dependency between threads and determine the proper thread mapping. [ABSTRACT FROM AUTHOR] |
| Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 128228884 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Hierarchical multicore thread mapping via estimation of remote communication. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Khaleghzadeh%2C+Hamidreza%22">Khaleghzadeh, Hamidreza</searchLink><relatesTo>1</relatesTo><i> hamidreza.khaleghzadeh@ucdconnect.ie</i><br /><searchLink fieldCode="AR" term="%22Deldari%2C+Hossein%22">Deldari, Hossein</searchLink><relatesTo>2</relatesTo><i> hdeldari@salman.ac.ir</i><br /><searchLink fieldCode="AR" term="%22Reddy%2C+Ravi%22">Reddy, Ravi</searchLink><relatesTo>1</relatesTo><i> ravi.manumachu@ucd.ie</i><br /><searchLink fieldCode="AR" term="%22Lastovetsky%2C+Alexey%22">Lastovetsky, Alexey</searchLink><relatesTo>1</relatesTo><i> alexey.lastovetsky@ucd.ie</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Journal+of+Supercomputing%22">Journal of Supercomputing</searchLink>. Mar2018, Vol. 74 Issue 3, p1321-1340. 20p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Multicore+processors%22">Multicore processors</searchLink><br /><searchLink fieldCode="DE" term="%22Threads+%28Computer+programs%29%22">Threads (Computer programs)</searchLink><br /><searchLink fieldCode="DE" term="%22Cache+memory%22">Cache memory</searchLink><br /><searchLink fieldCode="DE" term="%22Information+sharing%22">Information sharing</searchLink><br /><searchLink fieldCode="DE" term="%22Estimation+theory%22">Estimation theory</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Affinity-aware thread mapping is a method to effectively exploit cache resources in multicore processors. We propose an affinity- and architecture-aware thread mapping technique which maximizes data reuse and minimizes remote communications and cache coherency costs of multi-threaded applications. It consists of three main components: Data Sharing Estimator, Affine Mapping Finder and Maximum Speedup Predictor. Data Sharing Estimator creates application-specific data dependency signatures used by Affine Mapping Finder to determine the appropriate thread mapping of application for a given architecture. To prevent excessive thread migration, Maximum Speedup Predictor estimates the speedup of the obtained mapping and ignores it if it causes no significant performance improvement. The proposed framework is evaluated using Phoenix benchmark suite on two different multicore architectures. The proposed thread mapping approach gives 25% improvement in performance compared to default Linux scheduler. We also elucidate that affinity-based thread mapping approaches, which only consider the number of shared blocks, are not appropriate enough to accurately estimate data dependency between threads and determine the proper thread mapping. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s11227-017-2176-6 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 20 StartPage: 1321 Subjects: – SubjectFull: Multicore processors Type: general – SubjectFull: Threads (Computer programs) Type: general – SubjectFull: Cache memory Type: general – SubjectFull: Information sharing Type: general – SubjectFull: Estimation theory Type: general Titles: – TitleFull: Hierarchical multicore thread mapping via estimation of remote communication. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Khaleghzadeh, Hamidreza – PersonEntity: Name: NameFull: Deldari, Hossein – PersonEntity: Name: NameFull: Reddy, Ravi – PersonEntity: Name: NameFull: Lastovetsky, Alexey IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 03 Text: Mar2018 Type: published Y: 2018 Identifiers: – Type: issn-print Value: 09208542 Numbering: – Type: volume Value: 74 – Type: issue Value: 3 Titles: – TitleFull: Journal of Supercomputing Type: main |
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