Convolutional neural network acceleration with hardware/software co-design.
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| Title: | Convolutional neural network acceleration with hardware/software co-design. |
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| Authors: | Chen, Andrew Tzer-Yeu1 andrew.chen@auckland.ac.nz, Biglari-Abhari, Morteza1 m.abhari@auckland.ac.nz, Wang, Kevin I-Kai1 kevin.wang@auckland.ac.nz, Bouzerdoum, Abdesselam2,3 bouzer@uow.edu.au, Tivive, Fok Hing Chi2 tivive@uow.edu.au |
| Source: | Applied Intelligence. May2018, Vol. 48 Issue 5, p1288-1301. 14p. |
| Subjects: | Embedded computer systems, Graphics processing units, Field programmable gate arrays, Machine learning, Computer vision |
| Abstract: | Convolutional Neural Networks (CNNs) have a broad range of applications, such as image processing and natural language processing. Inspired by the mammalian visual cortex, CNNs have been shown to achieve impressive results on a number of computer vision challenges, but often with large amounts of processing power and no timing restrictions. This paper presents a design methodology for accelerating CNNs using Hardware/Software Co-design techniques, in order to balance performance and flexibility, particularly for resource-constrained systems. The methodology is applied to a gender recognition case study, using an ARM processor and FPGA fabric to create an embedded system that can process facial images in real-time. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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