Heterogeneous Von Neumann/Dataflow Microprocessors.
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| Title: | Heterogeneous Von Neumann/Dataflow Microprocessors. |
|---|---|
| Authors: | Nowatzki, Tony1 tjn@cs.ucla.edu, Gangadhar, Vinay2 vinay@cs.wisc.edu, Sankaralingam, Karthikeyan2 karu@cs.wisc.edu |
| Source: | Communications of the ACM. Jun2019, Vol. 62 Issue 6, p82-91. 9p. 5 Diagrams, 1 Chart, 5 Graphs. |
| Subjects: | Microprocessor design & construction, Microprocessor performance, Microprocessor energy consumption, Von Neumann architecture (Computers), Data flow computing |
| Abstract: | General-purpose processors (GPPs), which traditionally rely on a Von Neumann-based execution model, incur burdensome power overheads, largely due to the need to dynamically extract parallelism and maintain precise state. Further, it is extremely difficult to improve their performance without increasing energy usage. Decades-old explicit-dataflow architectures eliminate many Von Neumann overheads, but have not been successful as stand-alone alternatives because of poor performance on certain workloads, due to insufficient control speculation and communication overheads. We observe a synergy between out-of-order (OOO) and explicit-dataflow processors, whereby dynamically switching between them according to the behavior of program phases can greatly improve performance and energy efficiency. This work studies the potential of such a paradigm of heterogeneous execution models, by developing a specialization engine for explicit-dataflow (SEED) and integrating it with a standard out-of-order (OOO) core. When integrated with a dual-issue OOO, it becomes both faster (1.33×) and dramatically more energy efficient (1.70×). Integrated with an in-order core, it becomes faster than even a dual-issue OOO, with twice the energy efficiency. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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