Implementation of Low Power Null Conventional Logic Function for Configuration Logic Block.
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| Title: | Implementation of Low Power Null Conventional Logic Function for Configuration Logic Block. |
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| Authors: | Rajasekar, P.1 rajasekarkpr@gmail.com, Subash Kumar, C. S.2 subashkumarcs@gmail.com |
| Source: | Wireless Personal Communications. Aug2019, Vol. 107 Issue 4, p2231-2245. 15p. |
| Subjects: | Asynchronous circuits, Field programmable gate arrays |
| Abstract: | Todays, transistor level design plays major impact in the power consumption of the VLSI based design. The various logic design models are used to reduce the power consumption that includes synchronous and asynchronous design model. The operation of synchronous circuit is limited by the in phase factor of the clock pulse signal which is used to control the synchronous circuit. In contrast, asynchronous circuits are used widely because it causes low noise, require less power. It affects the less electromagnetic interference that allows reuse of the components. These asynchronous circuits are being implemented by Null Conventional Logic (NCL) which is a delay insensitive logic model. The Configuration Logic Block is the power consuming model in Field Programmable Gate Array (FPGA). This block contains the lookup table (LUT) and 27 fundamental NCL logic gates. To reduce the power consumption of this module, we use the Differential Cascade Voltage Switch Logic (DVSL). The power reduction is achieved in LUT by means of DVSL and minimizes the number transistors. This NCL, DVSL, FPGA logic element is simulated using 90 nm TSMC CMOS processing technology. [ABSTRACT FROM AUTHOR] |
| Copyright of Wireless Personal Communications is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 137908309 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Implementation of Low Power Null Conventional Logic Function for Configuration Logic Block. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Rajasekar%2C+P%2E%22">Rajasekar, P.</searchLink><relatesTo>1</relatesTo><i> rajasekarkpr@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Subash+Kumar%2C+C%2E+S%2E%22">Subash Kumar, C. S.</searchLink><relatesTo>2</relatesTo><i> subashkumarcs@gmail.com</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Wireless+Personal+Communications%22">Wireless Personal Communications</searchLink>. Aug2019, Vol. 107 Issue 4, p2231-2245. 15p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Asynchronous+circuits%22">Asynchronous circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Todays, transistor level design plays major impact in the power consumption of the VLSI based design. The various logic design models are used to reduce the power consumption that includes synchronous and asynchronous design model. The operation of synchronous circuit is limited by the in phase factor of the clock pulse signal which is used to control the synchronous circuit. In contrast, asynchronous circuits are used widely because it causes low noise, require less power. It affects the less electromagnetic interference that allows reuse of the components. These asynchronous circuits are being implemented by Null Conventional Logic (NCL) which is a delay insensitive logic model. The Configuration Logic Block is the power consuming model in Field Programmable Gate Array (FPGA). This block contains the lookup table (LUT) and 27 fundamental NCL logic gates. To reduce the power consumption of this module, we use the Differential Cascade Voltage Switch Logic (DVSL). The power reduction is achieved in LUT by means of DVSL and minimizes the number transistors. This NCL, DVSL, FPGA logic element is simulated using 90 nm TSMC CMOS processing technology. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Wireless Personal Communications is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s11277-019-06380-4 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 15 StartPage: 2231 Subjects: – SubjectFull: Asynchronous circuits Type: general – SubjectFull: Field programmable gate arrays Type: general Titles: – TitleFull: Implementation of Low Power Null Conventional Logic Function for Configuration Logic Block. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Rajasekar, P. – PersonEntity: Name: NameFull: Subash Kumar, C. S. IsPartOfRelationships: – BibEntity: Dates: – D: 15 M: 08 Text: Aug2019 Type: published Y: 2019 Identifiers: – Type: issn-print Value: 09296212 Numbering: – Type: volume Value: 107 – Type: issue Value: 4 Titles: – TitleFull: Wireless Personal Communications Type: main |
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