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An Accurate Worst Case Timing Analysis for RISC Processors.

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Title: An Accurate Worst Case Timing Analysis for RISC Processors.
Authors: Sung-Soo Lim1, Young Hyun Bae1, Gyu Tae Jang1, Byung-do Rhee1, Sang Lyul Min1 symin@dandclion.snu.ac.kr, Chang Yun Park2, Heonshik Shin1, Kunsoo Park1, Soo-Mook Moon3, Chong Sang Kim1
Source: IEEE Transactions on Software Engineering. Jul95, Vol. 21 Issue 7, p593-604. 12p. 10 Color Photographs, 11 Diagrams, 1 Chart.
Subjects: RISC microprocessors, Microprocessors, Computer storage devices, Software engineering, Computer software
Abstract: An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC's pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time-bound. In our approach, associated with each program construct is worst case timing abstraction, (WCTA), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning operations on WCTAs are newly defined to replace the add and max operations on time-bounds in the original timing schema. Our revised timing schema accurately accounts for the timing effects of pipelined execution and cache memory not only within but also across program constructs. This paper also reports on preliminary results of WCET analysis for a RISC processor. Our results show that tight WCET bounds (within a maximum of about 30% overestimation) can be obtained by using the revised timing schema approach. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Software Engineering is the property of IEEE Computer Society and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
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  Data: An Accurate Worst Case Timing Analysis for RISC Processors.
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  Data: <searchLink fieldCode="AR" term="%22Sung-Soo+Lim%22">Sung-Soo Lim</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Young+Hyun+Bae%22">Young Hyun Bae</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Gyu+Tae+Jang%22">Gyu Tae Jang</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Byung-do+Rhee%22">Byung-do Rhee</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Sang+Lyul+Min%22">Sang Lyul Min</searchLink><relatesTo>1</relatesTo><i> symin@dandclion.snu.ac.kr</i><br /><searchLink fieldCode="AR" term="%22Chang+Yun+Park%22">Chang Yun Park</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Heonshik+Shin%22">Heonshik Shin</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Kunsoo+Park%22">Kunsoo Park</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Soo-Mook+Moon%22">Soo-Mook Moon</searchLink><relatesTo>3</relatesTo><br /><searchLink fieldCode="AR" term="%22Chong+Sang+Kim%22">Chong Sang Kim</searchLink><relatesTo>1</relatesTo>
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  Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Software+Engineering%22">IEEE Transactions on Software Engineering</searchLink>. Jul95, Vol. 21 Issue 7, p593-604. 12p. 10 Color Photographs, 11 Diagrams, 1 Chart.
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  Data: An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC's pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time-bound. In our approach, associated with each program construct is worst case timing abstraction, (WCTA), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning operations on WCTAs are newly defined to replace the add and max operations on time-bounds in the original timing schema. Our revised timing schema accurately accounts for the timing effects of pipelined execution and cache memory not only within but also across program constructs. This paper also reports on preliminary results of WCET analysis for a RISC processor. Our results show that tight WCET bounds (within a maximum of about 30% overestimation) can be obtained by using the revised timing schema approach. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of IEEE Transactions on Software Engineering is the property of IEEE Computer Society and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/32.392980
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        Text: English
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      – SubjectFull: Computer storage devices
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              M: 07
              Text: Jul95
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              Y: 1995
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