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Architectural Supports for Block Ciphers in a RISC CPU Core by Instruction Overloading.

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Title: Architectural Supports for Block Ciphers in a RISC CPU Core by Instruction Overloading.
Authors: Choi, P.1 (AUTHOR) pjchoi@pknu.ac.kr, Kong, W.2 (AUTHOR) wbgong@hanyang.ac.kr, Kim, J.-H.3 (AUTHOR) jihoonkim@ewha.ac.kr, Lee, M.-K.4 (AUTHOR) mklee@inha.ac.kr, Kim, Dong Kyue2 (AUTHOR) dqkim@hanyang.ac.kr
Source: IEEE Transactions on Computers. Nov2022, Vol. 71 Issue 11, p2844-2857. 14p.
Subjects: Block ciphers, Central processing units, Reduced instruction set computers, Data encryption
Abstract: We propose a novel computer architectural concept of instruction overloading to support block ciphers. Instead of adding new instructions, we extend only the execution of some existing instructions. The proposed method allows a central processing unit core to execute different operations for the same instructions, depending on the address of the data, similar to operator overloading in object-oriented languages. We first present an extension for the AES algorithm, then we demonstrate its enhanced applicability with two further extensions supporting multiple block ciphers and hardware masking. The first extension for AES is also applicable to add/AND-rotate-XOR-based block ciphers such as SIMON. The AES and SIMON encryption speed, on this extended core, is at least doubled and is significantly less affected by memory latency. In addition, the AES encryption code requires only 18% of the memory of the previous software implementation. The second extension can further support various block ciphers defined over GF(28), and the SM4 encryption speed is increased by at least 182%. The third extension provides correlation power analysis (CPA) resistance with a 66.6% area overhead but almost no speed overhead, whereas a typical software anti-CPA AES implementation requires at least hundreds of times the execution time. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Computers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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DbLabel: Engineering Source
An: 160620851
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PubType: Academic Journal
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  Data: Architectural Supports for Block Ciphers in a RISC CPU Core by Instruction Overloading.
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  Data: <searchLink fieldCode="AR" term="%22Choi%2C+P%2E%22">Choi, P.</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> pjchoi@pknu.ac.kr</i><br /><searchLink fieldCode="AR" term="%22Kong%2C+W%2E%22">Kong, W.</searchLink><relatesTo>2</relatesTo> (AUTHOR)<i> wbgong@hanyang.ac.kr</i><br /><searchLink fieldCode="AR" term="%22Kim%2C+J%2E-H%2E%22">Kim, J.-H.</searchLink><relatesTo>3</relatesTo> (AUTHOR)<i> jihoonkim@ewha.ac.kr</i><br /><searchLink fieldCode="AR" term="%22Lee%2C+M%2E-K%2E%22">Lee, M.-K.</searchLink><relatesTo>4</relatesTo> (AUTHOR)<i> mklee@inha.ac.kr</i><br /><searchLink fieldCode="AR" term="%22Kim%2C+Dong+Kyue%22">Kim, Dong Kyue</searchLink><relatesTo>2</relatesTo> (AUTHOR)<i> dqkim@hanyang.ac.kr</i>
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  Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Computers%22">IEEE Transactions on Computers</searchLink>. Nov2022, Vol. 71 Issue 11, p2844-2857. 14p.
– Name: Subject
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  Data: <searchLink fieldCode="DE" term="%22Block+ciphers%22">Block ciphers</searchLink><br /><searchLink fieldCode="DE" term="%22Central+processing+units%22">Central processing units</searchLink><br /><searchLink fieldCode="DE" term="%22Reduced+instruction+set+computers%22">Reduced instruction set computers</searchLink><br /><searchLink fieldCode="DE" term="%22Data+encryption%22">Data encryption</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: We propose a novel computer architectural concept of instruction overloading to support block ciphers. Instead of adding new instructions, we extend only the execution of some existing instructions. The proposed method allows a central processing unit core to execute different operations for the same instructions, depending on the address of the data, similar to operator overloading in object-oriented languages. We first present an extension for the AES algorithm, then we demonstrate its enhanced applicability with two further extensions supporting multiple block ciphers and hardware masking. The first extension for AES is also applicable to add/AND-rotate-XOR-based block ciphers such as SIMON. The AES and SIMON encryption speed, on this extended core, is at least doubled and is significantly less affected by memory latency. In addition, the AES encryption code requires only 18% of the memory of the previous software implementation. The second extension can further support various block ciphers defined over GF(28), and the SM4 encryption speed is increased by at least 182%. The third extension provides correlation power analysis (CPA) resistance with a 66.6% area overhead but almost no speed overhead, whereas a typical software anti-CPA AES implementation requires at least hundreds of times the execution time. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
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  Data: <i>Copyright of IEEE Transactions on Computers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1109/TC.2021.3050515
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      – Code: eng
        Text: English
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        PageCount: 14
        StartPage: 2844
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      – SubjectFull: Block ciphers
        Type: general
      – SubjectFull: Central processing units
        Type: general
      – SubjectFull: Reduced instruction set computers
        Type: general
      – SubjectFull: Data encryption
        Type: general
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      – TitleFull: Architectural Supports for Block Ciphers in a RISC CPU Core by Instruction Overloading.
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              M: 11
              Text: Nov2022
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              Y: 2022
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