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Computation in the Context of Transport Triggered Architectures.

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Title: Computation in the Context of Transport Triggered Architectures.
Authors: Corporaal, Henk1 heco@cardit.et.tudelft.nl, Janssen, Johan1,2 johan@cardit.et.tudelft.nl, Arnold, Marnix1 marnix@cardit.et.tudelft.nl
Source: International Journal of Parallel Programming. Aug2000, Vol. 28 Issue 4, p401-427. 27p.
Subjects: Macro processors, Embedded computer systems -- Programming, Macroprogramming, Embedded computer systems, Parallel programming, Computer programming
Abstract: Processors used in embedded systems have specific requirements which are not always met by off-the-shelf processors. A templated processor architecture, which can easily be tuned towards a certain application (domain) offers a solution. The transport triggered architecture (TTA) template presented in this paper has a number of properties that make it very suitable for embedded system design. Key to its success is to give the compiler more control; it has to schedule all data transports within the processor. This paper highlights two important TTA-related issues. First a new code generation method for TTAs is discussed; it integrates scheduling and register allocation, thereby avoiding the notorious phase ordering problem between these two steps. Secondly, we discuss how to tune the instruction repertoire for an embedded processor. A tool is described which automatically detects frequent patterns of operations. These patterns can then be implemented on special function units. [ABSTRACT FROM AUTHOR]
Copyright of International Journal of Parallel Programming is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: <searchLink fieldCode="AR" term="%22Corporaal%2C+Henk%22">Corporaal, Henk</searchLink><relatesTo>1</relatesTo><i> heco@cardit.et.tudelft.nl</i><br /><searchLink fieldCode="AR" term="%22Janssen%2C+Johan%22">Janssen, Johan</searchLink><relatesTo>1,2</relatesTo><i> johan@cardit.et.tudelft.nl</i><br /><searchLink fieldCode="AR" term="%22Arnold%2C+Marnix%22">Arnold, Marnix</searchLink><relatesTo>1</relatesTo><i> marnix@cardit.et.tudelft.nl</i>
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  Data: <searchLink fieldCode="JN" term="%22International+Journal+of+Parallel+Programming%22">International Journal of Parallel Programming</searchLink>. Aug2000, Vol. 28 Issue 4, p401-427. 27p.
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  Data: <searchLink fieldCode="DE" term="%22Macro+processors%22">Macro processors</searchLink><br /><searchLink fieldCode="DE" term="%22Embedded+computer+systems+--+Programming%22">Embedded computer systems -- Programming</searchLink><br /><searchLink fieldCode="DE" term="%22Macroprogramming%22">Macroprogramming</searchLink><br /><searchLink fieldCode="DE" term="%22Embedded+computer+systems%22">Embedded computer systems</searchLink><br /><searchLink fieldCode="DE" term="%22Parallel+programming%22">Parallel programming</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+programming%22">Computer programming</searchLink>
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  Data: Processors used in embedded systems have specific requirements which are not always met by off-the-shelf processors. A templated processor architecture, which can easily be tuned towards a certain application (domain) offers a solution. The transport triggered architecture (TTA) template presented in this paper has a number of properties that make it very suitable for embedded system design. Key to its success is to give the compiler more control; it has to schedule all data transports within the processor. This paper highlights two important TTA-related issues. First a new code generation method for TTAs is discussed; it integrates scheduling and register allocation, thereby avoiding the notorious phase ordering problem between these two steps. Secondly, we discuss how to tune the instruction repertoire for an embedded processor. A tool is described which automatically detects frequent patterns of operations. These patterns can then be implemented on special function units. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of International Journal of Parallel Programming is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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              Text: Aug2000
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