Optimal sample length for efficient cache simulation
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| Title: | Optimal sample length for efficient cache simulation |
|---|---|
| Authors: | Eeckhout, Lieven1 leeckhou@elis.ugent.be, Niar, Smaïl2 smail.niar@univ-valenciennes.fr, De Bosschere, Koen1 kdb@elis.ugent.be |
| Source: | Journal of Systems Architecture. Sep2005, Vol. 51 Issue 9, p513-525. 13p. |
| Subjects: | Microprocessors, Microprocessor testing, Education, Algorithms |
| Abstract: | Abstract: Architectural simulations of microprocessors are extremely time-consuming nowadays due to the ever increasing complexity of current applications. In order to get realistic workloads on current hardware, benchmarks need to be constructed with huge dynamic instruction counts. For example, SPEC released the CPU2000 benchmark suite containing benchmarks that have a dynamic instruction count of several hundreds of billions of instructions. This is beneficial for real hardware evaluation. However, simulating these workloads is impractical if not impossible if we take into account that many simulation runs are needed in order to evaluate a large number of design points. Trace sampling is often used as a practical solution for this problem. In trace sampling, several representative samples are chosen from a real program trace. Since the sampled trace is much shorter than the original trace, a significant simulation speedup is obtained. In this paper, we study what is the optimal sample size to achieve a given level of accuracy while maximizing the total simulation speedup. From various experiments using SPEC CPU2000, we conclude that the optimal sample length (i) is not fixed over benchmarks, and (ii) increases with increasing warmup lengths. As such, we propose an algorithm that determines the optimal sample length per benchmark under different warmup scenarios. This is done within the context of sampled cache simulation. [Copyright &y& Elsevier] |
| Copyright of Journal of Systems Architecture is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 18244594 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Optimal sample length for efficient cache simulation – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Eeckhout%2C+Lieven%22">Eeckhout, Lieven</searchLink><relatesTo>1</relatesTo><i> leeckhou@elis.ugent.be</i><br /><searchLink fieldCode="AR" term="%22Niar%2C+Smaïl%22">Niar, Smaïl</searchLink><relatesTo>2</relatesTo><i> smail.niar@univ-valenciennes.fr</i><br /><searchLink fieldCode="AR" term="%22De+Bosschere%2C+Koen%22">De Bosschere, Koen</searchLink><relatesTo>1</relatesTo><i> kdb@elis.ugent.be</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Journal+of+Systems+Architecture%22">Journal of Systems Architecture</searchLink>. Sep2005, Vol. 51 Issue 9, p513-525. 13p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Microprocessors%22">Microprocessors</searchLink><br /><searchLink fieldCode="DE" term="%22Microprocessor+testing%22">Microprocessor testing</searchLink><br /><searchLink fieldCode="DE" term="%22Education%22">Education</searchLink><br /><searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Abstract: Architectural simulations of microprocessors are extremely time-consuming nowadays due to the ever increasing complexity of current applications. In order to get realistic workloads on current hardware, benchmarks need to be constructed with huge dynamic instruction counts. For example, SPEC released the CPU2000 benchmark suite containing benchmarks that have a dynamic instruction count of several hundreds of billions of instructions. This is beneficial for real hardware evaluation. However, simulating these workloads is impractical if not impossible if we take into account that many simulation runs are needed in order to evaluate a large number of design points. Trace sampling is often used as a practical solution for this problem. In trace sampling, several representative samples are chosen from a real program trace. Since the sampled trace is much shorter than the original trace, a significant simulation speedup is obtained. In this paper, we study what is the optimal sample size to achieve a given level of accuracy while maximizing the total simulation speedup. From various experiments using SPEC CPU2000, we conclude that the optimal sample length (i) is not fixed over benchmarks, and (ii) increases with increasing warmup lengths. As such, we propose an algorithm that determines the optimal sample length per benchmark under different warmup scenarios. This is done within the context of sampled cache simulation. [Copyright &y& Elsevier] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Journal of Systems Architecture is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1016/j.sysarc.2004.12.004 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 13 StartPage: 513 Subjects: – SubjectFull: Microprocessors Type: general – SubjectFull: Microprocessor testing Type: general – SubjectFull: Education Type: general – SubjectFull: Algorithms Type: general Titles: – TitleFull: Optimal sample length for efficient cache simulation Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Eeckhout, Lieven – PersonEntity: Name: NameFull: Niar, Smaïl – PersonEntity: Name: NameFull: De Bosschere, Koen IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 09 Text: Sep2005 Type: published Y: 2005 Identifiers: – Type: issn-print Value: 13837621 Numbering: – Type: volume Value: 51 – Type: issue Value: 9 Titles: – TitleFull: Journal of Systems Architecture Type: main |
| ResultId | 1 |
