APA (7th ed.) Citation

Rasheed, H. S., & Nelapati, R. P. (2025). Design of Hybrid CMOS-Memristor Combinational Circuits: Maximizing Efficiency with Low Power, Area, and Delay. Circuits, Systems & Signal Processing, 44(4), 2242. https://doi.org/10.1007/s00034-024-02935-4

Chicago Style (17th ed.) Citation

Rasheed, Haroon S., and Rajeev Pankaj Nelapati. "Design of Hybrid CMOS-Memristor Combinational Circuits: Maximizing Efficiency with Low Power, Area, and Delay." Circuits, Systems & Signal Processing 44, no. 4 (2025): 2242. https://doi.org/10.1007/s00034-024-02935-4.

MLA (9th ed.) Citation

Rasheed, Haroon S., and Rajeev Pankaj Nelapati. "Design of Hybrid CMOS-Memristor Combinational Circuits: Maximizing Efficiency with Low Power, Area, and Delay." Circuits, Systems & Signal Processing, vol. 44, no. 4, 2025, p. 2242, https://doi.org/10.1007/s00034-024-02935-4.