APA (7th ed.) Citation

Pavitra, Y. J., & Manikandan, J. (2025). Design of compressor-based multipliers using simulated annealing for arithmetic logic unit. Neural Computing & Applications, 37(33), 27747. https://doi.org/10.1007/s00521-025-10981-5

Chicago Style (17th ed.) Citation

Pavitra, Y. J., and J. Manikandan. "Design of Compressor-based Multipliers Using Simulated Annealing for Arithmetic Logic Unit." Neural Computing & Applications 37, no. 33 (2025): 27747. https://doi.org/10.1007/s00521-025-10981-5.

MLA (9th ed.) Citation

Pavitra, Y. J., and J. Manikandan. "Design of Compressor-based Multipliers Using Simulated Annealing for Arithmetic Logic Unit." Neural Computing & Applications, vol. 37, no. 33, 2025, p. 27747, https://doi.org/10.1007/s00521-025-10981-5.