Design of compressor-based multipliers using simulated annealing for arithmetic logic unit.
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| Title: | Design of compressor-based multipliers using simulated annealing for arithmetic logic unit. |
|---|---|
| Authors: | Pavitra, Y. J.1 (AUTHOR) pavitra.yj@pes.edu, Manikandan, J.1 (AUTHOR) |
| Source: | Neural Computing & Applications. Nov2025, Vol. 37 Issue 33, p27747-27757. 11p. |
| Subjects: | Simulated annealing, Computer arithmetic, Electronic circuit design, Mathematical optimization, Technical specifications, Field programmable gate arrays |
| Abstract: | Multipliers have complex structures and optimization of multiplier designs plays an important role in improving the performance parameters like area, power, and delay. A novel 4:2 counter-based compressor multipliers with pre-processing are proposed for the design of arithmetic and logic unit (ALU). Metaheuristics are widely used in finding various design alternatives to overcome the limitation of traditional approaches for circuit design. Arithmetic and logic unit is an important part of processing unit capable of performing various arithmetic and logical operations. Population-based simulated annealing is used for the design of ALU and two benchmark ALUs from LGSynth'91 are designed. Proposed work reduced the gate count by maximum of 51.83% and transistor count by 92.03% over baseline ALUs reported in literature. The flexibility to use different combination of resources allows us to propose various design alternatives. Functional units of proposed ALUs are designed using various resource types. A graphical user interface is developed for generation of Verilog scripts and test bench for verification of functional blocks. Proposed ALUs are synthesized on FPGA and Cadence Genus-90 nm standard cell library to compare with existing designs. With a speed increase of up to 54.95%, the proposed ALU outperformed traditional multiplier-based ALUs. Additionally, the suggested compressor-based ALU performed better, using 7.4% less power and increasing speed by 14.23%. [ABSTRACT FROM AUTHOR] |
| Copyright of Neural Computing & Applications is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 189054797 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Design of compressor-based multipliers using simulated annealing for arithmetic logic unit. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Pavitra%2C+Y%2E+J%2E%22">Pavitra, Y. J.</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> pavitra.yj@pes.edu</i><br /><searchLink fieldCode="AR" term="%22Manikandan%2C+J%2E%22">Manikandan, J.</searchLink><relatesTo>1</relatesTo> (AUTHOR) – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Neural+Computing+%26+Applications%22">Neural Computing & Applications</searchLink>. Nov2025, Vol. 37 Issue 33, p27747-27757. 11p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Simulated+annealing%22">Simulated annealing</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+arithmetic%22">Computer arithmetic</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+circuit+design%22">Electronic circuit design</searchLink><br /><searchLink fieldCode="DE" term="%22Mathematical+optimization%22">Mathematical optimization</searchLink><br /><searchLink fieldCode="DE" term="%22Technical+specifications%22">Technical specifications</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Multipliers have complex structures and optimization of multiplier designs plays an important role in improving the performance parameters like area, power, and delay. A novel 4:2 counter-based compressor multipliers with pre-processing are proposed for the design of arithmetic and logic unit (ALU). Metaheuristics are widely used in finding various design alternatives to overcome the limitation of traditional approaches for circuit design. Arithmetic and logic unit is an important part of processing unit capable of performing various arithmetic and logical operations. Population-based simulated annealing is used for the design of ALU and two benchmark ALUs from LGSynth'91 are designed. Proposed work reduced the gate count by maximum of 51.83% and transistor count by 92.03% over baseline ALUs reported in literature. The flexibility to use different combination of resources allows us to propose various design alternatives. Functional units of proposed ALUs are designed using various resource types. A graphical user interface is developed for generation of Verilog scripts and test bench for verification of functional blocks. Proposed ALUs are synthesized on FPGA and Cadence Genus-90 nm standard cell library to compare with existing designs. With a speed increase of up to 54.95%, the proposed ALU outperformed traditional multiplier-based ALUs. Additionally, the suggested compressor-based ALU performed better, using 7.4% less power and increasing speed by 14.23%. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Neural Computing & Applications is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s00521-025-10981-5 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 11 StartPage: 27747 Subjects: – SubjectFull: Simulated annealing Type: general – SubjectFull: Computer arithmetic Type: general – SubjectFull: Electronic circuit design Type: general – SubjectFull: Mathematical optimization Type: general – SubjectFull: Technical specifications Type: general – SubjectFull: Field programmable gate arrays Type: general Titles: – TitleFull: Design of compressor-based multipliers using simulated annealing for arithmetic logic unit. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Pavitra, Y. J. – PersonEntity: Name: NameFull: Manikandan, J. IsPartOfRelationships: – BibEntity: Dates: – D: 21 M: 11 Text: Nov2025 Type: published Y: 2025 Identifiers: – Type: issn-print Value: 09410643 Numbering: – Type: volume Value: 37 – Type: issue Value: 33 Titles: – TitleFull: Neural Computing & Applications Type: main |
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