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Energy‐Efficient and Area‐Optimized Reversible Carry Select Adder.

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Title: Energy‐Efficient and Area‐Optimized Reversible Carry Select Adder.
Authors: Murugesan, Praveena1 (AUTHOR) praveeias@yahoo.com, S., Palani2 (AUTHOR), V., Divya1 (AUTHOR), Soliman, Ahmed. M. (AUTHOR) soliman8@gmail.com
Source: IET Circuits, Devices & Systems (Wiley-Blackwell). 12/9/2025, Vol. 2025, p1-10. 10p.
Subjects: Reversible computing, Quantum computing, Digital technology, Energy consumption, Field programmable gate arrays, Very large scale circuit integration
Abstract: The carry select adder (CSA) is a highly efficient arithmetic component commonly utilized in digital systems due to its superior speed performance. In the context of energy‐efficient computing and fault‐tolerant quantum computing, reversible logic emerges as a critical technology owing to its potential to reduce energy dissipation by retaining information. This article introduces an efficient design for a reversible carry select adder (ERCSA), constructed using fundamental lossless logic gates such as modified TSG (MTSG), Peres, and Fredkin Gate (FRG). The proposed design eliminates the need to compute the carry for the default carry input of "1." Additionally, an optimized architecture is proposed to reduce the quantum cost of the circuit. The design achieves significant improvements by minimizing quantum cost, unused outputs, and gate count, while ensuring scalability for higher bit‐width additions. A comparative analysis with existing reversible adder highlights substantial performance enhancements, including reduction in the number of gates (35.4%), garbage outputs (18.9%), ancillary inputs (25%), quantum cost (22.7%), and delay (29.5%) compared to recent designs. The proposed architecture was modeled in Verilog and synthesized using Xilinx Vivado Design Suite targeting the Xilinx Artix‐7 FPGA family. The proposed 16‐bit ERCA architecture achieves 10.86% lower power, 76.43% reduced delay, and 21.7% better area efficiency compared to existing methods. These improvements make it highly suitable for low‐power and high‐speed VLSI applications. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
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Abstract:The carry select adder (CSA) is a highly efficient arithmetic component commonly utilized in digital systems due to its superior speed performance. In the context of energy‐efficient computing and fault‐tolerant quantum computing, reversible logic emerges as a critical technology owing to its potential to reduce energy dissipation by retaining information. This article introduces an efficient design for a reversible carry select adder (ERCSA), constructed using fundamental lossless logic gates such as modified TSG (MTSG), Peres, and Fredkin Gate (FRG). The proposed design eliminates the need to compute the carry for the default carry input of "1." Additionally, an optimized architecture is proposed to reduce the quantum cost of the circuit. The design achieves significant improvements by minimizing quantum cost, unused outputs, and gate count, while ensuring scalability for higher bit‐width additions. A comparative analysis with existing reversible adder highlights substantial performance enhancements, including reduction in the number of gates (35.4%), garbage outputs (18.9%), ancillary inputs (25%), quantum cost (22.7%), and delay (29.5%) compared to recent designs. The proposed architecture was modeled in Verilog and synthesized using Xilinx Vivado Design Suite targeting the Xilinx Artix‐7 FPGA family. The proposed 16‐bit ERCA architecture achieves 10.86% lower power, 76.43% reduced delay, and 21.7% better area efficiency compared to existing methods. These improvements make it highly suitable for low‐power and high‐speed VLSI applications. [ABSTRACT FROM AUTHOR]
ISSN:1751858X
DOI:10.1049/cds2/4179235