Energy‐Efficient and Area‐Optimized Reversible Carry Select Adder.
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| Title: | Energy‐Efficient and Area‐Optimized Reversible Carry Select Adder. |
|---|---|
| Authors: | Murugesan, Praveena1 (AUTHOR) praveeias@yahoo.com, S., Palani2 (AUTHOR), V., Divya1 (AUTHOR), Soliman, Ahmed. M. (AUTHOR) soliman8@gmail.com |
| Source: | IET Circuits, Devices & Systems (Wiley-Blackwell). 12/9/2025, Vol. 2025, p1-10. 10p. |
| Subjects: | Reversible computing, Quantum computing, Digital technology, Energy consumption, Field programmable gate arrays, Very large scale circuit integration |
| Abstract: | The carry select adder (CSA) is a highly efficient arithmetic component commonly utilized in digital systems due to its superior speed performance. In the context of energy‐efficient computing and fault‐tolerant quantum computing, reversible logic emerges as a critical technology owing to its potential to reduce energy dissipation by retaining information. This article introduces an efficient design for a reversible carry select adder (ERCSA), constructed using fundamental lossless logic gates such as modified TSG (MTSG), Peres, and Fredkin Gate (FRG). The proposed design eliminates the need to compute the carry for the default carry input of "1." Additionally, an optimized architecture is proposed to reduce the quantum cost of the circuit. The design achieves significant improvements by minimizing quantum cost, unused outputs, and gate count, while ensuring scalability for higher bit‐width additions. A comparative analysis with existing reversible adder highlights substantial performance enhancements, including reduction in the number of gates (35.4%), garbage outputs (18.9%), ancillary inputs (25%), quantum cost (22.7%), and delay (29.5%) compared to recent designs. The proposed architecture was modeled in Verilog and synthesized using Xilinx Vivado Design Suite targeting the Xilinx Artix‐7 FPGA family. The proposed 16‐bit ERCA architecture achieves 10.86% lower power, 76.43% reduced delay, and 21.7% better area efficiency compared to existing methods. These improvements make it highly suitable for low‐power and high‐speed VLSI applications. [ABSTRACT FROM AUTHOR] |
| Copyright of IET Circuits, Devices & Systems (Wiley-Blackwell) is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 189914088 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Energy‐Efficient and Area‐Optimized Reversible Carry Select Adder. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Murugesan%2C+Praveena%22">Murugesan, Praveena</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> praveeias@yahoo.com</i><br /><searchLink fieldCode="AR" term="%22S%2E%2C+Palani%22">S., Palani</searchLink><relatesTo>2</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22V%2E%2C+Divya%22">V., Divya</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Soliman%2C+Ahmed%2E+M%2E%22">Soliman, Ahmed. M.</searchLink> (AUTHOR)<i> soliman8@gmail.com</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IET+Circuits%2C+Devices+%26+Systems+%28Wiley-Blackwell%29%22">IET Circuits, Devices & Systems (Wiley-Blackwell)</searchLink>. 12/9/2025, Vol. 2025, p1-10. 10p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Reversible+computing%22">Reversible computing</searchLink><br /><searchLink fieldCode="DE" term="%22Quantum+computing%22">Quantum computing</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+technology%22">Digital technology</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+consumption%22">Energy consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Very+large+scale+circuit+integration%22">Very large scale circuit integration</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: The carry select adder (CSA) is a highly efficient arithmetic component commonly utilized in digital systems due to its superior speed performance. In the context of energy‐efficient computing and fault‐tolerant quantum computing, reversible logic emerges as a critical technology owing to its potential to reduce energy dissipation by retaining information. This article introduces an efficient design for a reversible carry select adder (ERCSA), constructed using fundamental lossless logic gates such as modified TSG (MTSG), Peres, and Fredkin Gate (FRG). The proposed design eliminates the need to compute the carry for the default carry input of "1." Additionally, an optimized architecture is proposed to reduce the quantum cost of the circuit. The design achieves significant improvements by minimizing quantum cost, unused outputs, and gate count, while ensuring scalability for higher bit‐width additions. A comparative analysis with existing reversible adder highlights substantial performance enhancements, including reduction in the number of gates (35.4%), garbage outputs (18.9%), ancillary inputs (25%), quantum cost (22.7%), and delay (29.5%) compared to recent designs. The proposed architecture was modeled in Verilog and synthesized using Xilinx Vivado Design Suite targeting the Xilinx Artix‐7 FPGA family. The proposed 16‐bit ERCA architecture achieves 10.86% lower power, 76.43% reduced delay, and 21.7% better area efficiency compared to existing methods. These improvements make it highly suitable for low‐power and high‐speed VLSI applications. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IET Circuits, Devices & Systems (Wiley-Blackwell) is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1049/cds2/4179235 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 10 StartPage: 1 Subjects: – SubjectFull: Reversible computing Type: general – SubjectFull: Quantum computing Type: general – SubjectFull: Digital technology Type: general – SubjectFull: Energy consumption Type: general – SubjectFull: Field programmable gate arrays Type: general – SubjectFull: Very large scale circuit integration Type: general Titles: – TitleFull: Energy‐Efficient and Area‐Optimized Reversible Carry Select Adder. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Murugesan, Praveena – PersonEntity: Name: NameFull: S., Palani – PersonEntity: Name: NameFull: V., Divya – PersonEntity: Name: NameFull: Soliman, Ahmed. M. IsPartOfRelationships: – BibEntity: Dates: – D: 09 M: 12 Text: 12/9/2025 Type: published Y: 2025 Identifiers: – Type: issn-print Value: 1751858X Numbering: – Type: volume Value: 2025 Titles: – TitleFull: IET Circuits, Devices & Systems (Wiley-Blackwell) Type: main |
| ResultId | 1 |
