Compact and High-Performance QCA-Based Adder Design Using an Optimized XOR Logic Structure.
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| Title: | Compact and High-Performance QCA-Based Adder Design Using an Optimized XOR Logic Structure. |
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| Authors: | BHUVANESWARI, V.1 bhuvanasrmist@gmail.com, YUVARAJ, S.2 |
| Source: | Technical Gazette / Tehnički Vjesnik. 2026, Vol. 33 Issue 1, p143-149. 7p. |
| Subjects: | Nanotechnology, Nanoelectronics, Digital electronics, Logic circuit design, Cellular automata, Computer logic, Scalability |
| Abstract: | Quantum-dot Cellular Automata (QCA) has emerged as a viable nanotechnology for implementing ultra-dense, low-power digital logic circuits, offering significant advantages over traditional CMOS technology in terms of power consumption and device scalability. This paper presents an efficient design approach for constructing QCA-based half adder and full adder circuits using a novel, highly compact XOR gate configuration. The proposed XOR gate requires only 8 quantum dots, which significantly reduces the overall complexity and area of the arithmetic circuits. The design methodology utilizes the concept of half-cell distance optimization and effective cell-to-cell interaction to achieve reduced latency and minimal crossover usage. The QCADesigner simulation tool is employed to validate the correctness and performance of the proposed circuits. Comparative analysis is carried out against previously reported QCA-based adder designs, considering key performance metrics such as cell count, number of wire-crossings, and propagation delay. The simulation results reveal that the proposed half adder and full adder designs outperform existing counterparts in terms of compactness and operational efficiency. Furthermore, the proposed layouts are fully planar and do not require multilayer crossovers, thereby simplifying fabrication and enhancing practical applicability. The findings demonstrate that the compact XOR gate-based approach provides a scalable and power-efficient solution for implementing fundamental arithmetic operations in future nanoelectronic systems. This work highlights the potential of QCA as a next-generation design paradigm for low-power computing architectures. [ABSTRACT FROM AUTHOR] |
| Copyright of Technical Gazette / Tehnički Vjesnik is the property of Tehnicki Vjesnik and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 190969693 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Compact and High-Performance QCA-Based Adder Design Using an Optimized XOR Logic Structure. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22BHUVANESWARI%2C+V%2E%22">BHUVANESWARI, V.</searchLink><relatesTo>1</relatesTo><i> bhuvanasrmist@gmail.com</i><br /><searchLink fieldCode="AR" term="%22YUVARAJ%2C+S%2E%22">YUVARAJ, S.</searchLink><relatesTo>2</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Technical+Gazette+%2F+Tehnički+Vjesnik%22">Technical Gazette / Tehnički Vjesnik</searchLink>. 2026, Vol. 33 Issue 1, p143-149. 7p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Nanotechnology%22">Nanotechnology</searchLink><br /><searchLink fieldCode="DE" term="%22Nanoelectronics%22">Nanoelectronics</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+electronics%22">Digital electronics</searchLink><br /><searchLink fieldCode="DE" term="%22Logic+circuit+design%22">Logic circuit design</searchLink><br /><searchLink fieldCode="DE" term="%22Cellular+automata%22">Cellular automata</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+logic%22">Computer logic</searchLink><br /><searchLink fieldCode="DE" term="%22Scalability%22">Scalability</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Quantum-dot Cellular Automata (QCA) has emerged as a viable nanotechnology for implementing ultra-dense, low-power digital logic circuits, offering significant advantages over traditional CMOS technology in terms of power consumption and device scalability. This paper presents an efficient design approach for constructing QCA-based half adder and full adder circuits using a novel, highly compact XOR gate configuration. The proposed XOR gate requires only 8 quantum dots, which significantly reduces the overall complexity and area of the arithmetic circuits. The design methodology utilizes the concept of half-cell distance optimization and effective cell-to-cell interaction to achieve reduced latency and minimal crossover usage. The QCADesigner simulation tool is employed to validate the correctness and performance of the proposed circuits. Comparative analysis is carried out against previously reported QCA-based adder designs, considering key performance metrics such as cell count, number of wire-crossings, and propagation delay. The simulation results reveal that the proposed half adder and full adder designs outperform existing counterparts in terms of compactness and operational efficiency. Furthermore, the proposed layouts are fully planar and do not require multilayer crossovers, thereby simplifying fabrication and enhancing practical applicability. The findings demonstrate that the compact XOR gate-based approach provides a scalable and power-efficient solution for implementing fundamental arithmetic operations in future nanoelectronic systems. This work highlights the potential of QCA as a next-generation design paradigm for low-power computing architectures. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Technical Gazette / Tehnički Vjesnik is the property of Tehnicki Vjesnik and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.17559/TV-20250406002559 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 7 StartPage: 143 Subjects: – SubjectFull: Nanotechnology Type: general – SubjectFull: Nanoelectronics Type: general – SubjectFull: Digital electronics Type: general – SubjectFull: Logic circuit design Type: general – SubjectFull: Cellular automata Type: general – SubjectFull: Computer logic Type: general – SubjectFull: Scalability Type: general Titles: – TitleFull: Compact and High-Performance QCA-Based Adder Design Using an Optimized XOR Logic Structure. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: BHUVANESWARI, V. – PersonEntity: Name: NameFull: YUVARAJ, S. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Text: 2026 Type: published Y: 2026 Identifiers: – Type: issn-print Value: 13303651 Numbering: – Type: volume Value: 33 – Type: issue Value: 1 Titles: – TitleFull: Technical Gazette / Tehnički Vjesnik Type: main |
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