APA (7th ed.) Citation

Naresh, K., Padma Sai, Y., Ganesh, C., & Majumdar, S. (2026). Design of Logic Level Pruning Approximate Arithmetic Circuits Using TIGFET. Circuits, Systems & Signal Processing, 45(1), 647. https://doi.org/10.1007/s00034-025-03102-z

Chicago Style (17th ed.) Citation

Naresh, Kattekola, Y. Padma Sai, Ch Ganesh, and Shubhankar Majumdar. "Design of Logic Level Pruning Approximate Arithmetic Circuits Using TIGFET." Circuits, Systems & Signal Processing 45, no. 1 (2026): 647. https://doi.org/10.1007/s00034-025-03102-z.

MLA (9th ed.) Citation

Naresh, Kattekola, et al. "Design of Logic Level Pruning Approximate Arithmetic Circuits Using TIGFET." Circuits, Systems & Signal Processing, vol. 45, no. 1, 2026, p. 647, https://doi.org/10.1007/s00034-025-03102-z.