Logical Fault Detection Approach for Mixed Control Flipping Faults in Reversible Circuits.
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| Title: | Logical Fault Detection Approach for Mixed Control Flipping Faults in Reversible Circuits. |
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| Authors: | Handique, Mousum1 (AUTHOR) mousum.smit@gmail.com, Prasad, Amrit2 (AUTHOR) amritpra94@gmail.com |
| Source: | IETE Journal of Research. Sep2025, Vol. 71 Issue 9, p3139-3155. 17p. |
| Subjects: | Reversible computing, Fault diagnosis, Digital electronics, Quantum computing |
| Abstract: | Due to the rapid development of computing machines in terms of micro-architectural designs, millions of transistors are involved per chip, which leads to complex digital circuit design and meets the demands of more computational power. It indicates that a single transistor's size is advancing at the atomic scale in future computing technologies. The gain of loss-less bit information in reversible logic computation is highly acceptable in modern computing devices. Therefore, motivated by these, researchers have explored the reversible logic concept for applying newer technologies such as quantum computing, optical computing, nanotechnology, DNA computing, digital communication systems, low-power CMOS design, etc. In the current literature, numerous developments on synthesis and optimization in reversible circuits have been proposed. Simultaneously, in order to observe the correct behavior of reversible circuits in terms of performing the correct functionality and integrity performance, testing plays an important role. In this article, we consider a fault model labeled the Mixed Control Flipping Fault (MixCFF) model that is applied in the reversible circuit, which is also relevant to the quantum circuits for representing the faults. The proposed work presents an automatic test pattern generation (ATPG) algorithm to detect the MixCFF. The proposed MixCFF model enables the correlation between the existing fault models in the reversible circuit, which are also presented in the proposed work. Experimental results are evaluated based on the MixCFF detection and the MixCFF fault coverage range with the help of different benchmark circuits using the suggested ATPG algorithm. [ABSTRACT FROM AUTHOR] |
| Copyright of IETE Journal of Research is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 191614866 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Logical Fault Detection Approach for Mixed Control Flipping Faults in Reversible Circuits. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Handique%2C+Mousum%22">Handique, Mousum</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> mousum.smit@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Prasad%2C+Amrit%22">Prasad, Amrit</searchLink><relatesTo>2</relatesTo> (AUTHOR)<i> amritpra94@gmail.com</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IETE+Journal+of+Research%22">IETE Journal of Research</searchLink>. Sep2025, Vol. 71 Issue 9, p3139-3155. 17p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Reversible+computing%22">Reversible computing</searchLink><br /><searchLink fieldCode="DE" term="%22Fault+diagnosis%22">Fault diagnosis</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+electronics%22">Digital electronics</searchLink><br /><searchLink fieldCode="DE" term="%22Quantum+computing%22">Quantum computing</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Due to the rapid development of computing machines in terms of micro-architectural designs, millions of transistors are involved per chip, which leads to complex digital circuit design and meets the demands of more computational power. It indicates that a single transistor's size is advancing at the atomic scale in future computing technologies. The gain of loss-less bit information in reversible logic computation is highly acceptable in modern computing devices. Therefore, motivated by these, researchers have explored the reversible logic concept for applying newer technologies such as quantum computing, optical computing, nanotechnology, DNA computing, digital communication systems, low-power CMOS design, etc. In the current literature, numerous developments on synthesis and optimization in reversible circuits have been proposed. Simultaneously, in order to observe the correct behavior of reversible circuits in terms of performing the correct functionality and integrity performance, testing plays an important role. In this article, we consider a fault model labeled the Mixed Control Flipping Fault (MixCFF) model that is applied in the reversible circuit, which is also relevant to the quantum circuits for representing the faults. The proposed work presents an automatic test pattern generation (ATPG) algorithm to detect the MixCFF. The proposed MixCFF model enables the correlation between the existing fault models in the reversible circuit, which are also presented in the proposed work. Experimental results are evaluated based on the MixCFF detection and the MixCFF fault coverage range with the help of different benchmark circuits using the suggested ATPG algorithm. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IETE Journal of Research is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1080/03772063.2025.2503340 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 17 StartPage: 3139 Subjects: – SubjectFull: Reversible computing Type: general – SubjectFull: Fault diagnosis Type: general – SubjectFull: Digital electronics Type: general – SubjectFull: Quantum computing Type: general Titles: – TitleFull: Logical Fault Detection Approach for Mixed Control Flipping Faults in Reversible Circuits. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Handique, Mousum – PersonEntity: Name: NameFull: Prasad, Amrit IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 09 Text: Sep2025 Type: published Y: 2025 Identifiers: – Type: issn-print Value: 03772063 Numbering: – Type: volume Value: 71 – Type: issue Value: 9 Titles: – TitleFull: IETE Journal of Research Type: main |
| ResultId | 1 |
