A Novel ALU Architecture Implementation using a Sub-Threshold Adiabatic Logic Design for Low-Power Processors.
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| Title: | A Novel ALU Architecture Implementation using a Sub-Threshold Adiabatic Logic Design for Low-Power Processors. |
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| Authors: | Anitha, A.1,2 (AUTHOR) aniravi08@gmail.com, Rooban, S.3 (AUTHOR) yes.rooban@gmail.com |
| Source: | IETE Journal of Research. Dec2025, Vol. 71 Issue 12, p4136-4152. 17p. |
| Subjects: | Microprocessor design & construction, Logic design, Semiconductor technology, Complementary metal oxide semiconductors, Very large scale circuit integration, Microprocessors, Energy consumption |
| Abstract: | The CMOS increases the power dissipation in the VLSI architectures due to the technology value going to deep submicron. Hence, power dissipation optimization in CMOS circuits is a trending research area. Novel techniques are introduced in the existing CMOS circuits to reduce power utilization. Adiabatic, subthreshold adiabatic, and mixed logics are some of the novel examples of reducing power. In this paper, the Sub-threshold Adiabatic Logic (SAL), along with other logic, is used to implement the high-speed and low-power Arithmetic-Logic Unit (ALU) for high-speed processor applications. All the arithmetic, control, and logic blocks are implemented by SAL and integrated for the architecture of a 4-bit ALU using Cadence Virtuoso tools with the 45 nm CMOS technology. The design metrics, such as area, delay, and power values, are compared with the conventional CMOS-based ALU architecture and existing ALU designs proposed by other researchers. The power of the proposed SAL-ALU and mixed design-based ALU is decreased by 25% and 34% to the conventional CMOS-ALU. The power of the mixed design-based ALU is decreased by 11% compared to the SAL-ALU architecture. The transistor count of the proposed ALU is reduced by 64% by SAL-ALU and 77% by mixed design-based ALU, respectively. The mixed design-based ALU needed 38% transistors than the SAL-ALU architecture. The delay of the proposed SAL-ALU and mixed design-ALU is reduced by almost 65% compared to the conventional CMOS-ALU. [ABSTRACT FROM AUTHOR] |
| Copyright of IETE Journal of Research is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 193014896 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: A Novel ALU Architecture Implementation using a Sub-Threshold Adiabatic Logic Design for Low-Power Processors. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Anitha%2C+A%2E%22">Anitha, A.</searchLink><relatesTo>1,2</relatesTo> (AUTHOR)<i> aniravi08@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Rooban%2C+S%2E%22">Rooban, S.</searchLink><relatesTo>3</relatesTo> (AUTHOR)<i> yes.rooban@gmail.com</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IETE+Journal+of+Research%22">IETE Journal of Research</searchLink>. Dec2025, Vol. 71 Issue 12, p4136-4152. 17p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Microprocessor+design+%26+construction%22">Microprocessor design & construction</searchLink><br /><searchLink fieldCode="DE" term="%22Logic+design%22">Logic design</searchLink><br /><searchLink fieldCode="DE" term="%22Semiconductor+technology%22">Semiconductor technology</searchLink><br /><searchLink fieldCode="DE" term="%22Complementary+metal+oxide+semiconductors%22">Complementary metal oxide semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Very+large+scale+circuit+integration%22">Very large scale circuit integration</searchLink><br /><searchLink fieldCode="DE" term="%22Microprocessors%22">Microprocessors</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+consumption%22">Energy consumption</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: The CMOS increases the power dissipation in the VLSI architectures due to the technology value going to deep submicron. Hence, power dissipation optimization in CMOS circuits is a trending research area. Novel techniques are introduced in the existing CMOS circuits to reduce power utilization. Adiabatic, subthreshold adiabatic, and mixed logics are some of the novel examples of reducing power. In this paper, the Sub-threshold Adiabatic Logic (SAL), along with other logic, is used to implement the high-speed and low-power Arithmetic-Logic Unit (ALU) for high-speed processor applications. All the arithmetic, control, and logic blocks are implemented by SAL and integrated for the architecture of a 4-bit ALU using Cadence Virtuoso tools with the 45 nm CMOS technology. The design metrics, such as area, delay, and power values, are compared with the conventional CMOS-based ALU architecture and existing ALU designs proposed by other researchers. The power of the proposed SAL-ALU and mixed design-based ALU is decreased by 25% and 34% to the conventional CMOS-ALU. The power of the mixed design-based ALU is decreased by 11% compared to the SAL-ALU architecture. The transistor count of the proposed ALU is reduced by 64% by SAL-ALU and 77% by mixed design-based ALU, respectively. The mixed design-based ALU needed 38% transistors than the SAL-ALU architecture. The delay of the proposed SAL-ALU and mixed design-ALU is reduced by almost 65% compared to the conventional CMOS-ALU. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IETE Journal of Research is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1080/03772063.2025.2546580 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 17 StartPage: 4136 Subjects: – SubjectFull: Microprocessor design & construction Type: general – SubjectFull: Logic design Type: general – SubjectFull: Semiconductor technology Type: general – SubjectFull: Complementary metal oxide semiconductors Type: general – SubjectFull: Very large scale circuit integration Type: general – SubjectFull: Microprocessors Type: general – SubjectFull: Energy consumption Type: general Titles: – TitleFull: A Novel ALU Architecture Implementation using a Sub-Threshold Adiabatic Logic Design for Low-Power Processors. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Anitha, A. – PersonEntity: Name: NameFull: Rooban, S. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 12 Text: Dec2025 Type: published Y: 2025 Identifiers: – Type: issn-print Value: 03772063 Numbering: – Type: volume Value: 71 – Type: issue Value: 12 Titles: – TitleFull: IETE Journal of Research Type: main |
| ResultId | 1 |
