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A Novel ALU Architecture Implementation using a Sub-Threshold Adiabatic Logic Design for Low-Power Processors.

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Title: A Novel ALU Architecture Implementation using a Sub-Threshold Adiabatic Logic Design for Low-Power Processors.
Authors: Anitha, A.1,2 (AUTHOR) aniravi08@gmail.com, Rooban, S.3 (AUTHOR) yes.rooban@gmail.com
Source: IETE Journal of Research. Dec2025, Vol. 71 Issue 12, p4136-4152. 17p.
Subjects: Microprocessor design & construction, Logic design, Semiconductor technology, Complementary metal oxide semiconductors, Very large scale circuit integration, Microprocessors, Energy consumption
Abstract: The CMOS increases the power dissipation in the VLSI architectures due to the technology value going to deep submicron. Hence, power dissipation optimization in CMOS circuits is a trending research area. Novel techniques are introduced in the existing CMOS circuits to reduce power utilization. Adiabatic, subthreshold adiabatic, and mixed logics are some of the novel examples of reducing power. In this paper, the Sub-threshold Adiabatic Logic (SAL), along with other logic, is used to implement the high-speed and low-power Arithmetic-Logic Unit (ALU) for high-speed processor applications. All the arithmetic, control, and logic blocks are implemented by SAL and integrated for the architecture of a 4-bit ALU using Cadence Virtuoso tools with the 45 nm CMOS technology. The design metrics, such as area, delay, and power values, are compared with the conventional CMOS-based ALU architecture and existing ALU designs proposed by other researchers. The power of the proposed SAL-ALU and mixed design-based ALU is decreased by 25% and 34% to the conventional CMOS-ALU. The power of the mixed design-based ALU is decreased by 11% compared to the SAL-ALU architecture. The transistor count of the proposed ALU is reduced by 64% by SAL-ALU and 77% by mixed design-based ALU, respectively. The mixed design-based ALU needed 38% transistors than the SAL-ALU architecture. The delay of the proposed SAL-ALU and mixed design-ALU is reduced by almost 65% compared to the conventional CMOS-ALU. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:The CMOS increases the power dissipation in the VLSI architectures due to the technology value going to deep submicron. Hence, power dissipation optimization in CMOS circuits is a trending research area. Novel techniques are introduced in the existing CMOS circuits to reduce power utilization. Adiabatic, subthreshold adiabatic, and mixed logics are some of the novel examples of reducing power. In this paper, the Sub-threshold Adiabatic Logic (SAL), along with other logic, is used to implement the high-speed and low-power Arithmetic-Logic Unit (ALU) for high-speed processor applications. All the arithmetic, control, and logic blocks are implemented by SAL and integrated for the architecture of a 4-bit ALU using Cadence Virtuoso tools with the 45 nm CMOS technology. The design metrics, such as area, delay, and power values, are compared with the conventional CMOS-based ALU architecture and existing ALU designs proposed by other researchers. The power of the proposed SAL-ALU and mixed design-based ALU is decreased by 25% and 34% to the conventional CMOS-ALU. The power of the mixed design-based ALU is decreased by 11% compared to the SAL-ALU architecture. The transistor count of the proposed ALU is reduced by 64% by SAL-ALU and 77% by mixed design-based ALU, respectively. The mixed design-based ALU needed 38% transistors than the SAL-ALU architecture. The delay of the proposed SAL-ALU and mixed design-ALU is reduced by almost 65% compared to the conventional CMOS-ALU. [ABSTRACT FROM AUTHOR]
ISSN:03772063
DOI:10.1080/03772063.2025.2546580