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An Optimized Reversible Multiplier with Sklansky Adder for Next-Generation ALUs.

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Title: An Optimized Reversible Multiplier with Sklansky Adder for Next-Generation ALUs.
Authors: Yadav, Rishu1 (AUTHOR) rishuyadav21@iiitp.ac.in, Kushwaha, Nagendra1 (AUTHOR) nagendra@iiitp.ac.in, Mishra, Sandeep2 (AUTHOR) sandeepmishra@eced.svnit.ac.in, Ranjan Kumar, Ashish1 (AUTHOR) ashish.ranjanc2s@iiitp.ac.in
Source: IETE Journal of Research. Jan-Jun2026, Vol. 72 Issue 1, p271-283. 13p.
Subjects: Reversible computing, Computer arithmetic, Systems on a chip, Field programmable gate arrays, Power aware computing
Abstract: The rising demand for high-performance and low-power consumption in modern computing devices is making the method of Arithmetic Logic Units (ALUs) a critical area of focus. This paper introduces a novel reversible multiplier architecture integrated with a Sklansky adder, specifically designed to address the challenges of modern ALUs, such as power reduction, low propagation delay and efficient resource utilization. By leveraging the parallel prefix efficiency of the Sklansky adder and the inherent power-saving capabilities of reversible logic, the proposed architecture achieves superior performance metrics. Synthesized and evaluated on the ARTIX-7 FPGA (XC7a35tcpg236-1) using VHDL in Xilinx Vivado, the design demonstrates a propagation delay of 6.458 ns, a power consumption of 26.442 µW, and a power-delay product (PDP) of 170.762 fJ. These results significantly outperform existing designs, highlighting the architecture's scalability and suitability for compact, low-power System-on-Chip (SoC) applications. This work sets a new benchmark in reversible logic-based ALU design, paving the way for advanced, energy-efficient computing platforms. [ABSTRACT FROM AUTHOR]
Copyright of IETE Journal of Research is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
An: 193754109
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  Label: Title
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  Data: An Optimized Reversible Multiplier with Sklansky Adder for Next-Generation ALUs.
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  Data: <searchLink fieldCode="AR" term="%22Yadav%2C+Rishu%22">Yadav, Rishu</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> rishuyadav21@iiitp.ac.in</i><br /><searchLink fieldCode="AR" term="%22Kushwaha%2C+Nagendra%22">Kushwaha, Nagendra</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> nagendra@iiitp.ac.in</i><br /><searchLink fieldCode="AR" term="%22Mishra%2C+Sandeep%22">Mishra, Sandeep</searchLink><relatesTo>2</relatesTo> (AUTHOR)<i> sandeepmishra@eced.svnit.ac.in</i><br /><searchLink fieldCode="AR" term="%22Ranjan+Kumar%2C+Ashish%22">Ranjan Kumar, Ashish</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> ashish.ranjanc2s@iiitp.ac.in</i>
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  Data: <searchLink fieldCode="JN" term="%22IETE+Journal+of+Research%22">IETE Journal of Research</searchLink>. Jan-Jun2026, Vol. 72 Issue 1, p271-283. 13p.
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  Data: <searchLink fieldCode="DE" term="%22Reversible+computing%22">Reversible computing</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+arithmetic%22">Computer arithmetic</searchLink><br /><searchLink fieldCode="DE" term="%22Systems+on+a+chip%22">Systems on a chip</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Power+aware+computing%22">Power aware computing</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: The rising demand for high-performance and low-power consumption in modern computing devices is making the method of Arithmetic Logic Units (ALUs) a critical area of focus. This paper introduces a novel reversible multiplier architecture integrated with a Sklansky adder, specifically designed to address the challenges of modern ALUs, such as power reduction, low propagation delay and efficient resource utilization. By leveraging the parallel prefix efficiency of the Sklansky adder and the inherent power-saving capabilities of reversible logic, the proposed architecture achieves superior performance metrics. Synthesized and evaluated on the ARTIX-7 FPGA (XC7a35tcpg236-1) using VHDL in Xilinx Vivado, the design demonstrates a propagation delay of 6.458 ns, a power consumption of 26.442 µW, and a power-delay product (PDP) of 170.762 fJ. These results significantly outperform existing designs, highlighting the architecture's scalability and suitability for compact, low-power System-on-Chip (SoC) applications. This work sets a new benchmark in reversible logic-based ALU design, paving the way for advanced, energy-efficient computing platforms. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of IETE Journal of Research is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1080/03772063.2025.2559729
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      – Code: eng
        Text: English
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        PageCount: 13
        StartPage: 271
    Subjects:
      – SubjectFull: Reversible computing
        Type: general
      – SubjectFull: Computer arithmetic
        Type: general
      – SubjectFull: Systems on a chip
        Type: general
      – SubjectFull: Field programmable gate arrays
        Type: general
      – SubjectFull: Power aware computing
        Type: general
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      – TitleFull: An Optimized Reversible Multiplier with Sklansky Adder for Next-Generation ALUs.
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            NameFull: Yadav, Rishu
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            NameFull: Kushwaha, Nagendra
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            NameFull: Mishra, Sandeep
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            NameFull: Ranjan Kumar, Ashish
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            – D: 01
              M: 01
              Text: Jan-Jun2026
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              Y: 2026
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