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基于可重构低功耗处理的高速乘法器设计.

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Title: 基于可重构低功耗处理的高速乘法器设计.
Alternate Title: A high-speed multiplier based on reconfigurable low-power processig.
Authors: 陈一凡1 624817308@qq.com, 杨宇恒2 yangyuheng@kkchips.com, 姜岩峰1 jiangyf@jiangnan.edu.cn, 蔡孟冶1 caimengye@jiangnan.edu.cn
Source: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Apr2026, Vol. 48 Issue 4, p608-616. 9p.
Subjects: Encoding, Computer performance
Abstract (English): To address the issues of high latency and high-power consumption associated with traditional radix-4 Booth-encoded multipliers, this paper introduces the implementation of a low-power, high-speed multiplier based on an improved Booth encoding scheme. The multiplier employs an improved radix-4 Booth encoding method and utilizes an advance zero encoding module to mitigate power losses caused by conventional encoding. Additionally, a preprocessing approach is adopted to increase extension sign bits, thereby reducing critical path delay. By optimizing the generation rules for the partial product array, the number of compressors is reduced. Furthermore, through enhancements to the compressor structure and the adoption of a reconfigurable compression design, the critical path is shortened, leading to a reduction in overall power consumption of the compression tree. The designed multiplier is implemented using 180 nm process and synthesized with Design Compiler. For a 32-bit multiplier employing this architecture, the critical path delay is 6.73 ns, the circuit area is 116 736 μm2, and the overall power consumption, obtained through random generation of 5 000 sets of random numbers, is 13 838 μW. [ABSTRACT FROM AUTHOR]
Abstract (Chinese): 针对传统radix-4 Booth编码乘法器所导致的高延迟和高功耗,设计并实现了一种改进型 radix-4 Booth编码的低功耗高速乘法器。该乘法器采用改进型radix-4 Booth编码,通过超前置零编码模 块改善了原有编码带来的功耗损失,并采用预处理方法增加扩展符号位,减小关键路径延迟;通过优化生 成规则部分积阵列,减少压缩器数量;通过改进压缩器结构和可重构压缩设计缩短关键路径长度,降低压 缩树整体功耗。所设计的乘法器采用180 nm 工艺完成设计,通过Design Compiler进行综合,采用该结 构32位乘法器关键路径延迟为6.73 ns,电路面积为116 736 μm2,通过随机产生5 000组随机数得到整 体功耗为13 838 μW。. [ABSTRACT FROM AUTHOR]
Copyright of Computer Engineering & Science / Jisuanji Gongcheng yu Kexue is the property of Computer Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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  – Type: pdflink
Text:
  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 193831503
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: 基于可重构低功耗处理的高速乘法器设计.
– Name: TitleAlt
  Label: Alternate Title
  Group: TiAlt
  Data: A high-speed multiplier based on reconfigurable low-power processig.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22陈一凡%22">陈一凡</searchLink><relatesTo>1</relatesTo><i> 624817308@qq.com</i><br /><searchLink fieldCode="AR" term="%22杨宇恒%22">杨宇恒</searchLink><relatesTo>2</relatesTo><i> yangyuheng@kkchips.com</i><br /><searchLink fieldCode="AR" term="%22姜岩峰%22">姜岩峰</searchLink><relatesTo>1</relatesTo><i> jiangyf@jiangnan.edu.cn</i><br /><searchLink fieldCode="AR" term="%22蔡孟冶%22">蔡孟冶</searchLink><relatesTo>1</relatesTo><i> caimengye@jiangnan.edu.cn</i>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Computer+Engineering+%26+Science+%2F+Jisuanji+Gongcheng+yu+Kexue%22">Computer Engineering & Science / Jisuanji Gongcheng yu Kexue</searchLink>. Apr2026, Vol. 48 Issue 4, p608-616. 9p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Encoding%22">Encoding</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+performance%22">Computer performance</searchLink>
– Name: Abstract
  Label: Abstract (English)
  Group: Ab
  Data: To address the issues of high latency and high-power consumption associated with traditional radix-4 Booth-encoded multipliers, this paper introduces the implementation of a low-power, high-speed multiplier based on an improved Booth encoding scheme. The multiplier employs an improved radix-4 Booth encoding method and utilizes an advance zero encoding module to mitigate power losses caused by conventional encoding. Additionally, a preprocessing approach is adopted to increase extension sign bits, thereby reducing critical path delay. By optimizing the generation rules for the partial product array, the number of compressors is reduced. Furthermore, through enhancements to the compressor structure and the adoption of a reconfigurable compression design, the critical path is shortened, leading to a reduction in overall power consumption of the compression tree. The designed multiplier is implemented using 180 nm process and synthesized with Design Compiler. For a 32-bit multiplier employing this architecture, the critical path delay is 6.73 ns, the circuit area is 116 736 μm2, and the overall power consumption, obtained through random generation of 5 000 sets of random numbers, is 13 838 μW. [ABSTRACT FROM AUTHOR]
– Name: Abstract
  Label: Abstract (Chinese)
  Group: Ab
  Data: 针对传统radix-4 Booth编码乘法器所导致的高延迟和高功耗,设计并实现了一种改进型 radix-4 Booth编码的低功耗高速乘法器。该乘法器采用改进型radix-4 Booth编码,通过超前置零编码模 块改善了原有编码带来的功耗损失,并采用预处理方法增加扩展符号位,减小关键路径延迟;通过优化生 成规则部分积阵列,减少压缩器数量;通过改进压缩器结构和可重构压缩设计缩短关键路径长度,降低压 缩树整体功耗。所设计的乘法器采用180 nm 工艺完成设计,通过Design Compiler进行综合,采用该结 构32位乘法器关键路径延迟为6.73 ns,电路面积为116 736 μm2,通过随机产生5 000组随机数得到整 体功耗为13 838 μW。. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Computer Engineering & Science / Jisuanji Gongcheng yu Kexue is the property of Computer Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.3969/j.issn.1007-130X.2026.04.005
    Languages:
      – Code: chi
        Text: Chinese
    PhysicalDescription:
      Pagination:
        PageCount: 9
        StartPage: 608
    Subjects:
      – SubjectFull: Encoding
        Type: general
      – SubjectFull: Computer performance
        Type: general
    Titles:
      – TitleFull: 基于可重构低功耗处理的高速乘法器设计.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: 陈一凡
      – PersonEntity:
          Name:
            NameFull: 杨宇恒
      – PersonEntity:
          Name:
            NameFull: 姜岩峰
      – PersonEntity:
          Name:
            NameFull: 蔡孟冶
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 04
              Text: Apr2026
              Type: published
              Y: 2026
          Identifiers:
            – Type: issn-print
              Value: 1007130X
          Numbering:
            – Type: volume
              Value: 48
            – Type: issue
              Value: 4
          Titles:
            – TitleFull: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue
              Type: main
ResultId 1