APA (7th ed.) Citation

Chen, J., Fu, Y., Lian, Y., Han, J., Pi, J., & Ling, M. (2026). A novel RISC-V core for the networking processing processor with bit-level custom instructions and thread-aware fetching architecture. Integration: The VLSI Journal, 109, N.PAG. https://doi.org/10.1016/j.vlsi.2026.102749

Chicago Style (17th ed.) Citation

Chen, Jiakun, Yuanming Fu, Yuyu Lian, Jianhui Han, Jianyuan Pi, and Ming Ling. "A Novel RISC-V Core for the Networking Processing Processor with Bit-level Custom Instructions and Thread-aware Fetching Architecture." Integration: The VLSI Journal 109 (2026): N.PAG. https://doi.org/10.1016/j.vlsi.2026.102749.

MLA (9th ed.) Citation

Chen, Jiakun, et al. "A Novel RISC-V Core for the Networking Processing Processor with Bit-level Custom Instructions and Thread-aware Fetching Architecture." Integration: The VLSI Journal, vol. 109, 2026, p. N.PAG, https://doi.org/10.1016/j.vlsi.2026.102749.