A 75-dB Image Rejection IF-Input Quadrature-Sampling SC ΣΔ Modulator.
Saved in:
| Title: | A 75-dB Image Rejection IF-Input Quadrature-Sampling SC ΣΔ Modulator. |
|---|---|
| Authors: | Kong-Pang Pun1 kppun@ee.cuhk.edu.hk, Wang-Tung Cheng1, Chiu-Sing Choy1, Cheong-Fat Chan1 |
| Source: | IEEE Journal of Solid-State Circuits. Jun2006, Vol. 41 Issue 6, p1353-1363. 11p. 4 Black and White Photographs, 10 Diagrams, 2 Charts, 5 Graphs. |
| Subjects: | Intermediate frequency amplifiers, Capacitors, Electronic modulators, Electric circuits, Digital-to-analog converters, Bandwidths |
| Abstract: | Quadrature sampling of intermediate frequency (IF) signals is subject to the well-known problem of gain and phase mismatches between the in-phase (I) and quadrature (Q) channels. This paper presents an IF-input quadrature-sampling switched-capacitor (SC) ΣΔ A modulator that circumvents the I/Q mismatch problem by time-sharing between the I and Q channels the critical circuit components, namely, the sampling capacitor and the capacitor of the first-stage feedback digital-to-analog converter (DAC). In addition, a clocking scheme that is insensitive to I/Q phase imbalance is used. A third-order single-loop 1-bit low-pass modulator has been designed and fabricated in a 0.35-μm CMOS process with an active area of 0.57 mm². The experimental results show that the modulator achieves an image-rejection ratio (IRR) of greater than 75 dB throughout a 200-kHz signal bandwidth. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
|---|---|
| Header | DbId: egs DbLabel: Engineering Source An: 21347867 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
| IllustrationInfo | |
| Items | – Name: Title Label: Title Group: Ti Data: A 75-dB Image Rejection IF-Input Quadrature-Sampling SC ΣΔ Modulator. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Kong-Pang+Pun%22">Kong-Pang Pun</searchLink><relatesTo>1</relatesTo><i> kppun@ee.cuhk.edu.hk</i><br /><searchLink fieldCode="AR" term="%22Wang-Tung+Cheng%22">Wang-Tung Cheng</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Chiu-Sing+Choy%22">Chiu-Sing Choy</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Cheong-Fat+Chan%22">Cheong-Fat Chan</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Journal+of+Solid-State+Circuits%22">IEEE Journal of Solid-State Circuits</searchLink>. Jun2006, Vol. 41 Issue 6, p1353-1363. 11p. 4 Black and White Photographs, 10 Diagrams, 2 Charts, 5 Graphs. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Intermediate+frequency+amplifiers%22">Intermediate frequency amplifiers</searchLink><br /><searchLink fieldCode="DE" term="%22Capacitors%22">Capacitors</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+modulators%22">Electronic modulators</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+circuits%22">Electric circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Digital-to-analog+converters%22">Digital-to-analog converters</searchLink><br /><searchLink fieldCode="DE" term="%22Bandwidths%22">Bandwidths</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Quadrature sampling of intermediate frequency (IF) signals is subject to the well-known problem of gain and phase mismatches between the in-phase (I) and quadrature (Q) channels. This paper presents an IF-input quadrature-sampling switched-capacitor (SC) ΣΔ A modulator that circumvents the I/Q mismatch problem by time-sharing between the I and Q channels the critical circuit components, namely, the sampling capacitor and the capacitor of the first-stage feedback digital-to-analog converter (DAC). In addition, a clocking scheme that is insensitive to I/Q phase imbalance is used. A third-order single-loop 1-bit low-pass modulator has been designed and fabricated in a 0.35-μm CMOS process with an active area of 0.57 mm². The experimental results show that the modulator achieves an image-rejection ratio (IRR) of greater than 75 dB throughout a 200-kHz signal bandwidth. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=21347867 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/JSSC.2006.874252 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 11 StartPage: 1353 Subjects: – SubjectFull: Intermediate frequency amplifiers Type: general – SubjectFull: Capacitors Type: general – SubjectFull: Electronic modulators Type: general – SubjectFull: Electric circuits Type: general – SubjectFull: Digital-to-analog converters Type: general – SubjectFull: Bandwidths Type: general Titles: – TitleFull: A 75-dB Image Rejection IF-Input Quadrature-Sampling SC ΣΔ Modulator. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Kong-Pang Pun – PersonEntity: Name: NameFull: Wang-Tung Cheng – PersonEntity: Name: NameFull: Chiu-Sing Choy – PersonEntity: Name: NameFull: Cheong-Fat Chan IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 06 Text: Jun2006 Type: published Y: 2006 Identifiers: – Type: issn-print Value: 00189200 Numbering: – Type: volume Value: 41 – Type: issue Value: 6 Titles: – TitleFull: IEEE Journal of Solid-State Circuits Type: main |
| ResultId | 1 |
