A 75-dB Image Rejection IF-Input Quadrature-Sampling SC ΣΔ Modulator.
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| Title: | A 75-dB Image Rejection IF-Input Quadrature-Sampling SC ΣΔ Modulator. |
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| Authors: | Kong-Pang Pun1 kppun@ee.cuhk.edu.hk, Wang-Tung Cheng1, Chiu-Sing Choy1, Cheong-Fat Chan1 |
| Source: | IEEE Journal of Solid-State Circuits. Jun2006, Vol. 41 Issue 6, p1353-1363. 11p. 4 Black and White Photographs, 10 Diagrams, 2 Charts, 5 Graphs. |
| Subjects: | Intermediate frequency amplifiers, Capacitors, Electronic modulators, Electric circuits, Digital-to-analog converters, Bandwidths |
| Abstract: | Quadrature sampling of intermediate frequency (IF) signals is subject to the well-known problem of gain and phase mismatches between the in-phase (I) and quadrature (Q) channels. This paper presents an IF-input quadrature-sampling switched-capacitor (SC) ΣΔ A modulator that circumvents the I/Q mismatch problem by time-sharing between the I and Q channels the critical circuit components, namely, the sampling capacitor and the capacitor of the first-stage feedback digital-to-analog converter (DAC). In addition, a clocking scheme that is insensitive to I/Q phase imbalance is used. A third-order single-loop 1-bit low-pass modulator has been designed and fabricated in a 0.35-μm CMOS process with an active area of 0.57 mm². The experimental results show that the modulator achieves an image-rejection ratio (IRR) of greater than 75 dB throughout a 200-kHz signal bandwidth. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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