View in EDS PDF Full Text

Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture.

Saved in:
Bibliographic Details
Title: Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture.
Authors: Abderazek, Ben Abdallah1 benab@u-aizu.ac.jp, Masuda, Masashi1, Canedo, Arquimedes1,2, Kuroda, Kenichi1
Source: Journal of Supercomputing. Sep2011, Vol. 57 Issue 3, p314-338. 25p.
Subjects: Parallelizing compilers, Queueing networks, Code generators, High performance processors, RISC microprocessors
Abstract: This work presents a static method implemented in a compiler for extracting high instruction level parallelism for the 32-bit QueueCore, a queue computation-based processor. The instructions of a queue processor implicitly read and write their operands, making instructions short and the programs free of false dependencies. This characteristic allows the exploitation of maximum parallelism and improves code density. Compiling for the QueueCore requires a new approach since the concept of registers disappears. We propose a new efficient code generation algorithm for the QueueCore. For a set of numerical benchmark programs, our compiler extracts more parallelism than the optimizing compiler for an RISC machine by a factor of 1.38. Through the use of QueueCore's reduced instruction set, we are able to generate 20% and 26% denser code than two embedded RISC processors. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
FullText Links:
  – Type: pdflink
Text:
  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 63540809
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Abderazek%2C+Ben+Abdallah%22">Abderazek, Ben Abdallah</searchLink><relatesTo>1</relatesTo><i> benab@u-aizu.ac.jp</i><br /><searchLink fieldCode="AR" term="%22Masuda%2C+Masashi%22">Masuda, Masashi</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Canedo%2C+Arquimedes%22">Canedo, Arquimedes</searchLink><relatesTo>1,2</relatesTo><br /><searchLink fieldCode="AR" term="%22Kuroda%2C+Kenichi%22">Kuroda, Kenichi</searchLink><relatesTo>1</relatesTo>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Journal+of+Supercomputing%22">Journal of Supercomputing</searchLink>. Sep2011, Vol. 57 Issue 3, p314-338. 25p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Parallelizing+compilers%22">Parallelizing compilers</searchLink><br /><searchLink fieldCode="DE" term="%22Queueing+networks%22">Queueing networks</searchLink><br /><searchLink fieldCode="DE" term="%22Code+generators%22">Code generators</searchLink><br /><searchLink fieldCode="DE" term="%22High+performance+processors%22">High performance processors</searchLink><br /><searchLink fieldCode="DE" term="%22RISC+microprocessors%22">RISC microprocessors</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: This work presents a static method implemented in a compiler for extracting high instruction level parallelism for the 32-bit QueueCore, a queue computation-based processor. The instructions of a queue processor implicitly read and write their operands, making instructions short and the programs free of false dependencies. This characteristic allows the exploitation of maximum parallelism and improves code density. Compiling for the QueueCore requires a new approach since the concept of registers disappears. We propose a new efficient code generation algorithm for the QueueCore. For a set of numerical benchmark programs, our compiler extracts more parallelism than the optimizing compiler for an RISC machine by a factor of 1.38. Through the use of QueueCore's reduced instruction set, we are able to generate 20% and 26% denser code than two embedded RISC processors. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=63540809
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1007/s11227-010-0409-z
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 25
        StartPage: 314
    Subjects:
      – SubjectFull: Parallelizing compilers
        Type: general
      – SubjectFull: Queueing networks
        Type: general
      – SubjectFull: Code generators
        Type: general
      – SubjectFull: High performance processors
        Type: general
      – SubjectFull: RISC microprocessors
        Type: general
    Titles:
      – TitleFull: Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Abderazek, Ben Abdallah
      – PersonEntity:
          Name:
            NameFull: Masuda, Masashi
      – PersonEntity:
          Name:
            NameFull: Canedo, Arquimedes
      – PersonEntity:
          Name:
            NameFull: Kuroda, Kenichi
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 09
              Text: Sep2011
              Type: published
              Y: 2011
          Identifiers:
            – Type: issn-print
              Value: 09208542
          Numbering:
            – Type: volume
              Value: 57
            – Type: issue
              Value: 3
          Titles:
            – TitleFull: Journal of Supercomputing
              Type: main
ResultId 1