Utilizing Faulty Cores.
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| Title: | Utilizing Faulty Cores. |
|---|---|
| Authors: | Raghavan, Karthik1 karthrags@gmail.com, Veezhinathan, Kamakoti1 kama@cse.iitm.ac.in |
| Source: | IETE Technical Review. Sep/Oct2011, Vol. 28 Issue 5, p400-408. 9p. 2 Diagrams. |
| Subjects: | Semiconductors, Manufacturing processes, Lithography, Production methods, Semiconductor industry |
| Abstract: | Hard errors may be caused during the semiconductor manufacturing process, or in the field due to wearout. The incidence of such defects is increasing with the increasing complexity of lithography and reducing feature sizes. The naive solution to this problem is to discard or disable the faulty chip, but this strategy is very suboptimal. In many cases, there is scope for extracting something of value from a faulty chip. This has spurred research into recovering chips that have failed due to hard errors. This is a survey of the contributions made in this very relevant area of research, with a brief look at recent trends in detecting and diagnosing faults. [ABSTRACT FROM AUTHOR] |
| Copyright of IETE Technical Review is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 67254579 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Utilizing Faulty Cores. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Raghavan%2C+Karthik%22">Raghavan, Karthik</searchLink><relatesTo>1</relatesTo><i> karthrags@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Veezhinathan%2C+Kamakoti%22">Veezhinathan, Kamakoti</searchLink><relatesTo>1</relatesTo><i> kama@cse.iitm.ac.in</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IETE+Technical+Review%22">IETE Technical Review</searchLink>. Sep/Oct2011, Vol. 28 Issue 5, p400-408. 9p. 2 Diagrams. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Semiconductors%22">Semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Manufacturing+processes%22">Manufacturing processes</searchLink><br /><searchLink fieldCode="DE" term="%22Lithography%22">Lithography</searchLink><br /><searchLink fieldCode="DE" term="%22Production+methods%22">Production methods</searchLink><br /><searchLink fieldCode="DE" term="%22Semiconductor+industry%22">Semiconductor industry</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Hard errors may be caused during the semiconductor manufacturing process, or in the field due to wearout. The incidence of such defects is increasing with the increasing complexity of lithography and reducing feature sizes. The naive solution to this problem is to discard or disable the faulty chip, but this strategy is very suboptimal. In many cases, there is scope for extracting something of value from a faulty chip. This has spurred research into recovering chips that have failed due to hard errors. This is a survey of the contributions made in this very relevant area of research, with a brief look at recent trends in detecting and diagnosing faults. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IETE Technical Review is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.4103/0256-4602.85972 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 9 StartPage: 400 Subjects: – SubjectFull: Semiconductors Type: general – SubjectFull: Manufacturing processes Type: general – SubjectFull: Lithography Type: general – SubjectFull: Production methods Type: general – SubjectFull: Semiconductor industry Type: general Titles: – TitleFull: Utilizing Faulty Cores. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Raghavan, Karthik – PersonEntity: Name: NameFull: Veezhinathan, Kamakoti IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 09 Text: Sep/Oct2011 Type: published Y: 2011 Identifiers: – Type: issn-print Value: 02564602 Numbering: – Type: volume Value: 28 – Type: issue Value: 5 Titles: – TitleFull: IETE Technical Review Type: main |
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