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Resource-Efficient FPGA Architecture and Implementation of Hough Transform.

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Title: Resource-Efficient FPGA Architecture and Implementation of Hough Transform.
Authors: Chen, Zhong-Ho1, Su, Alvin W. Y.1, Sun, Ming-Ting2
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Aug2012, Vol. 20 Issue 8, p1419-1428. 10p.
Subjects: Field programmable gate arrays, Integrated circuit design, Mathematical transformations, Embedded computer systems, Parallel algorithms, Image analysis
Abstract: Hough transform is widely used for detecting straight lines in an image, but it involves huge computations. For embedded application, field-programmable gate arrays are one of the most used hardware accelerators to achieve real-time implementation of Hough transform. In this paper, we present a resource-efficient architecture and implementation of Hough transform on an FPGA. The incrementing property of Hough transform is described and used to reduce the resource requirement. In order to facilitate parallelism, we divide the image into blocks and apply the incrementing property to pixels within a block and between blocks. Moreover, the locality of Hough transform is analyzed to reduce the memory access. The proposed architecture is implement on an Altera EP2S180F1508C3 device and can operate at a maximum frequency of 200 MHz. It could compute the Hough transform of 512 \times 512 test images with 180 orientations in 2.07–3.16 ms without using many FPGA resources (i.e., one could achieve the performance by adopting a low-cost low-end FPGA). [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: <searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuit+design%22">Integrated circuit design</searchLink><br /><searchLink fieldCode="DE" term="%22Mathematical+transformations%22">Mathematical transformations</searchLink><br /><searchLink fieldCode="DE" term="%22Embedded+computer+systems%22">Embedded computer systems</searchLink><br /><searchLink fieldCode="DE" term="%22Parallel+algorithms%22">Parallel algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Image+analysis%22">Image analysis</searchLink>
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  Data: Hough transform is widely used for detecting straight lines in an image, but it involves huge computations. For embedded application, field-programmable gate arrays are one of the most used hardware accelerators to achieve real-time implementation of Hough transform. In this paper, we present a resource-efficient architecture and implementation of Hough transform on an FPGA. The incrementing property of Hough transform is described and used to reduce the resource requirement. In order to facilitate parallelism, we divide the image into blocks and apply the incrementing property to pixels within a block and between blocks. Moreover, the locality of Hough transform is analyzed to reduce the memory access. The proposed architecture is implement on an Altera EP2S180F1508C3 device and can operate at a maximum frequency of 200 MHz. It could compute the Hough transform of 512 \times 512 test images with 180 orientations in 2.07–3.16 ms without using many FPGA resources (i.e., one could achieve the performance by adopting a low-cost low-end FPGA). [ABSTRACT FROM PUBLISHER]
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  Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/TVLSI.2011.2160002
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      – SubjectFull: Integrated circuit design
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      – SubjectFull: Mathematical transformations
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      – SubjectFull: Embedded computer systems
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      – SubjectFull: Parallel algorithms
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              Text: Aug2012
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