Bibliographic Details
| Title: |
Network-on-chips on 3-D ICs: Past, Present, and Future. |
| Authors: |
Pawan Kumar, M.1 mpkpawan@cse.iitm.ac.in, Murali, Srinivasan1 srinivasan.murali@epfl.ch, Veezhinathan, Kamakoti1 kama@cse.iitm.ac.in |
| Source: |
IETE Technical Review. Jul/Aug2012, Vol. 29 Issue 4, p318-335. 18p. 11 Diagrams. |
| Subjects: |
Networks on a chip, Three-dimensional integrated circuits, Transistors, Computer-aided design, Network routers, Semiconductors, Scalability |
| Abstract: |
Interconnects have become the chief bottleneck in today's era of chip design. Along the road of interconnect evolution, Network-on-Chips (NoCs) have emerged as a structured and scalable solution for connecting computational elements on a very large scale integration chip. Also, with the deep-submicron technology allowing integration of billions of transistors, chips have grown very complex and large in size. The global wire-length problem was addressed with the integration of devices in the third dimension (3-D). The combination of 3-D integration and a scalable interconnect, like NoCs, promise to revolutionize design for Chip Multi-processors, System-on-chips, and System-in-package. This paper surveys on all the advancements in 3-D NoCs. [ABSTRACT FROM AUTHOR] |
|
Copyright of IETE Technical Review is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) |
| Database: |
Engineering Source |
