Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction.
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| Title: | Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction. |
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| Authors: | Fojtik, Matthew1, Fick, David1, Kim, Yejoong1, Pinckney, Nathaniel1, Harris, David Money2, Blaauw, David1, Sylvester, Dennis1 |
| Source: | IEEE Journal of Solid-State Circuits. Jan2013, Vol. 48 Issue 1, p66-81. 16p. |
| Subjects: | Random access memory, Time delay systems, Complementary metal oxide semiconductors, Computer architecture, Systems design, Energy consumption |
| Abstract: | We propose Bubble Razor, an architecturally independent approach to timing error detection and correction that avoids hold-time issues and enables large timing speculation windows. A local stalling technique that can be automatically inserted into any design allows the system to scale to larger processors. We implemented Bubble Razor on an ARM Cortex-M3 microprocessor in 45 nm CMOS without detailed knowledge of its internal architecture to demonstrate the technique's automated capability. The flip-flop based design was converted to two-phase latch timing using commercial retiming tools; Bubble Razor was then inserted using automatic scripts. This system marks the first published implementation of a Razor-style scheme on a complete, commercial processor. It provides an energy efficiency improvement of 60% or a throughput gain of up to 100% compared to operating with worst case timing margins. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 84636274 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Fojtik%2C+Matthew%22">Fojtik, Matthew</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Fick%2C+David%22">Fick, David</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Kim%2C+Yejoong%22">Kim, Yejoong</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Pinckney%2C+Nathaniel%22">Pinckney, Nathaniel</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Harris%2C+David+Money%22">Harris, David Money</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Blaauw%2C+David%22">Blaauw, David</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Sylvester%2C+Dennis%22">Sylvester, Dennis</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Journal+of+Solid-State+Circuits%22">IEEE Journal of Solid-State Circuits</searchLink>. Jan2013, Vol. 48 Issue 1, p66-81. 16p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Random+access+memory%22">Random access memory</searchLink><br /><searchLink fieldCode="DE" term="%22Time+delay+systems%22">Time delay systems</searchLink><br /><searchLink fieldCode="DE" term="%22Complementary+metal+oxide+semiconductors%22">Complementary metal oxide semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+architecture%22">Computer architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Systems+design%22">Systems design</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+consumption%22">Energy consumption</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: We propose Bubble Razor, an architecturally independent approach to timing error detection and correction that avoids hold-time issues and enables large timing speculation windows. A local stalling technique that can be automatically inserted into any design allows the system to scale to larger processors. We implemented Bubble Razor on an ARM Cortex-M3 microprocessor in 45 nm CMOS without detailed knowledge of its internal architecture to demonstrate the technique's automated capability. The flip-flop based design was converted to two-phase latch timing using commercial retiming tools; Bubble Razor was then inserted using automatic scripts. This system marks the first published implementation of a Razor-style scheme on a complete, commercial processor. It provides an energy efficiency improvement of 60% or a throughput gain of up to 100% compared to operating with worst case timing margins. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/JSSC.2012.2220912 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 16 StartPage: 66 Subjects: – SubjectFull: Random access memory Type: general – SubjectFull: Time delay systems Type: general – SubjectFull: Complementary metal oxide semiconductors Type: general – SubjectFull: Computer architecture Type: general – SubjectFull: Systems design Type: general – SubjectFull: Energy consumption Type: general Titles: – TitleFull: Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Fojtik, Matthew – PersonEntity: Name: NameFull: Fick, David – PersonEntity: Name: NameFull: Kim, Yejoong – PersonEntity: Name: NameFull: Pinckney, Nathaniel – PersonEntity: Name: NameFull: Harris, David Money – PersonEntity: Name: NameFull: Blaauw, David – PersonEntity: Name: NameFull: Sylvester, Dennis IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Text: Jan2013 Type: published Y: 2013 Identifiers: – Type: issn-print Value: 00189200 Numbering: – Type: volume Value: 48 – Type: issue Value: 1 Titles: – TitleFull: IEEE Journal of Solid-State Circuits Type: main |
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