Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction.
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| Title: | Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction. |
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| Authors: | Fojtik, Matthew1, Fick, David1, Kim, Yejoong1, Pinckney, Nathaniel1, Harris, David Money2, Blaauw, David1, Sylvester, Dennis1 |
| Source: | IEEE Journal of Solid-State Circuits. Jan2013, Vol. 48 Issue 1, p66-81. 16p. |
| Subjects: | Random access memory, Time delay systems, Complementary metal oxide semiconductors, Computer architecture, Systems design, Energy consumption |
| Abstract: | We propose Bubble Razor, an architecturally independent approach to timing error detection and correction that avoids hold-time issues and enables large timing speculation windows. A local stalling technique that can be automatically inserted into any design allows the system to scale to larger processors. We implemented Bubble Razor on an ARM Cortex-M3 microprocessor in 45 nm CMOS without detailed knowledge of its internal architecture to demonstrate the technique's automated capability. The flip-flop based design was converted to two-phase latch timing using commercial retiming tools; Bubble Razor was then inserted using automatic scripts. This system marks the first published implementation of a Razor-style scheme on a complete, commercial processor. It provides an energy efficiency improvement of 60% or a throughput gain of up to 100% compared to operating with worst case timing margins. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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