Design and Implementation of Low Power Generic Reversible Binary-Coded Decimal Adder on Artix-7 FPGA.
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| Title: | Design and Implementation of Low Power Generic Reversible Binary-Coded Decimal Adder on Artix-7 FPGA. |
|---|---|
| Authors: | Tiwari, Kanchan S.1 (AUTHOR) kanchan.tiwari@mescoepune.org, Wahul, Revati M.2 (AUTHOR), Shinde, Sagar D.3 (AUTHOR), Dudhedia, Manisha A.4 (AUTHOR), Gaikwad, Varsha P.5 (AUTHOR), Bhalerao, Pranav1 (AUTHOR), Gill, Simrit Kaur1 (AUTHOR), Chhajed, Neeraj1 (AUTHOR), Daniel, Christy1 (AUTHOR), Gawande, Shravan H.6 (AUTHOR) |
| Source: | Mathematical Modelling of Engineering Problems. Feb2025, Vol. 12 Issue 2, p730-744. 15p. |
| Database: | Mathematics Source |
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| Header | DbId: msf DbLabel: Mathematics Source An: 183462368 AccessLevel: 2 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Design and Implementation of Low Power Generic Reversible Binary-Coded Decimal Adder on Artix-7 FPGA. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Tiwari%2C+Kanchan+S%2E%22">Tiwari, Kanchan S.</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> kanchan.tiwari@mescoepune.org</i><br /><searchLink fieldCode="AR" term="%22Wahul%2C+Revati+M%2E%22">Wahul, Revati M.</searchLink><relatesTo>2</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Shinde%2C+Sagar+D%2E%22">Shinde, Sagar D.</searchLink><relatesTo>3</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Dudhedia%2C+Manisha+A%2E%22">Dudhedia, Manisha A.</searchLink><relatesTo>4</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Gaikwad%2C+Varsha+P%2E%22">Gaikwad, Varsha P.</searchLink><relatesTo>5</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Bhalerao%2C+Pranav%22">Bhalerao, Pranav</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Gill%2C+Simrit+Kaur%22">Gill, Simrit Kaur</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Chhajed%2C+Neeraj%22">Chhajed, Neeraj</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Daniel%2C+Christy%22">Daniel, Christy</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Gawande%2C+Shravan+H%2E%22">Gawande, Shravan H.</searchLink><relatesTo>6</relatesTo> (AUTHOR) – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Mathematical+Modelling+of+Engineering+Problems%22">Mathematical Modelling of Engineering Problems</searchLink>. Feb2025, Vol. 12 Issue 2, p730-744. 15p. |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=msf&AN=183462368 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.18280/mmep.120235 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 15 StartPage: 730 Titles: – TitleFull: Design and Implementation of Low Power Generic Reversible Binary-Coded Decimal Adder on Artix-7 FPGA. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Tiwari, Kanchan S. – PersonEntity: Name: NameFull: Wahul, Revati M. – PersonEntity: Name: NameFull: Shinde, Sagar D. – PersonEntity: Name: NameFull: Dudhedia, Manisha A. – PersonEntity: Name: NameFull: Gaikwad, Varsha P. – PersonEntity: Name: NameFull: Bhalerao, Pranav – PersonEntity: Name: NameFull: Gill, Simrit Kaur – PersonEntity: Name: NameFull: Chhajed, Neeraj – PersonEntity: Name: NameFull: Daniel, Christy – PersonEntity: Name: NameFull: Gawande, Shravan H. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 02 Text: Feb2025 Type: published Y: 2025 Identifiers: – Type: issn-print Value: 23690739 Numbering: – Type: volume Value: 12 – Type: issue Value: 2 Titles: – TitleFull: Mathematical Modelling of Engineering Problems Type: main |
| ResultId | 1 |
