Design and Implementation of Low Power Generic Reversible Binary-Coded Decimal Adder on Artix-7 FPGA.
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| Title: | Design and Implementation of Low Power Generic Reversible Binary-Coded Decimal Adder on Artix-7 FPGA. |
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| Authors: | Tiwari, Kanchan S.1 (AUTHOR) kanchan.tiwari@mescoepune.org, Wahul, Revati M.2 (AUTHOR), Shinde, Sagar D.3 (AUTHOR), Dudhedia, Manisha A.4 (AUTHOR), Gaikwad, Varsha P.5 (AUTHOR), Bhalerao, Pranav1 (AUTHOR), Gill, Simrit Kaur1 (AUTHOR), Chhajed, Neeraj1 (AUTHOR), Daniel, Christy1 (AUTHOR), Gawande, Shravan H.6 (AUTHOR) |
| Source: | Mathematical Modelling of Engineering Problems. Feb2025, Vol. 12 Issue 2, p730-744. 15p. |
| Database: | Mathematics Source |
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