Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder.
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| Title: | Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder. |
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| Authors: | Singhal, Subodh Kumar1, subodh.singhal@juet.ac.in, Mohanty, B. K.2, basantkumar.mohanty@nmims.edu, Patel, Sujit Kumar3, sujit.patel@thapar.edu, Saxena, Gaurav4, gaurav.saxena@juet.ac.in |
| Source: | Journal of Circuits, Systems & Computers; Oct2020, Vol. 29 Issue 12, pN.PAG-N.PAG, 20p |
| Database: | Applied Science & Technology Source |
| ISSN: | 02181266 |
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| DOI: | 10.1142/S0218126620501868 |
