APA (7th ed.) Citation

Singhal, S. K., Mohanty, B. K., Patel, S. K., & Saxena, G. (2020). Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder. Journal of Circuits, Systems & Computers, 29(12), N.PAG. https://doi.org/10.1142/S0218126620501868

Chicago Style (17th ed.) Citation

Singhal, Subodh Kumar, B. K. Mohanty, Sujit Kumar Patel, and Gaurav Saxena. "Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder." Journal of Circuits, Systems & Computers 29, no. 12 (2020): N.PAG. https://doi.org/10.1142/S0218126620501868.

MLA (9th ed.) Citation

Singhal, Subodh Kumar, et al. "Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder." Journal of Circuits, Systems & Computers, vol. 29, no. 12, 2020, p. N.PAG, https://doi.org/10.1142/S0218126620501868.