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Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder.

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Title: Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder.
Authors: Singhal, Subodh Kumar1, subodh.singhal@juet.ac.in, Mohanty, B. K.2, basantkumar.mohanty@nmims.edu, Patel, Sujit Kumar3, sujit.patel@thapar.edu, Saxena, Gaurav4, gaurav.saxena@juet.ac.in
Source: Journal of Circuits, Systems & Computers; Oct2020, Vol. 29 Issue 12, pN.PAG-N.PAG, 20p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 146196861
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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      – Type: doi
        Value: 10.1142/S0218126620501868
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      – Code: eng
        Text: English
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        PageCount: 20
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      – TitleFull: Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder.
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            NameFull: Singhal, Subodh Kumar
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            NameFull: Mohanty, B. K.
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              Text: Oct2020
              Type: published
              Y: 2020
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              Value: 29
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              Value: 12
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