Path delay test generation at functional level.
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| Title: | Path delay test generation at functional level. |
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| Authors: | Bareisa, Eduardas1, Jusas, Vacius1, vacius.jusas@ktu.lt, Motiejunas, Kestutis1, Seinauskas, Rimantas1 |
| Source: | IET Computers & Digital Techniques (Wiley-Blackwell); May2015, Vol. 9 Issue 3, p135-141, 7p |
| Database: | Applied Science & Technology Source |
| ISSN: | 17518601 |
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| DOI: | 10.1049/iet-cdt.2013.0096 |
