APA (7th ed.) Citation

Bareisa, E., Jusas, V., Motiejunas, K., & Seinauskas, R. (2015). Path delay test generation at functional level. IET Computers & Digital Techniques (Wiley-Blackwell), 9(3), 135. https://doi.org/10.1049/iet-cdt.2013.0096

Chicago Style (17th ed.) Citation

Bareisa, Eduardas, Vacius Jusas, Kestutis Motiejunas, and Rimantas Seinauskas. "Path Delay Test Generation at Functional Level." IET Computers & Digital Techniques (Wiley-Blackwell) 9, no. 3 (2015): 135. https://doi.org/10.1049/iet-cdt.2013.0096.

MLA (9th ed.) Citation

Bareisa, Eduardas, et al. "Path Delay Test Generation at Functional Level." IET Computers & Digital Techniques (Wiley-Blackwell), vol. 9, no. 3, 2015, p. 135, https://doi.org/10.1049/iet-cdt.2013.0096.