Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design Exploration.
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| Title: | Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design Exploration. |
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| Authors: | Chauviere, Baudouin1, baudouin.chauviere@utah.edukstevens@ece.utah.edu, Stevens, Kenneth S.1 |
| Source: | Journal of Low Power Electronics & Applications; Sep2024, Vol. 14 Issue 3, p44, 16p |
| Database: | Applied Science & Technology Source |
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| ISSN: | 20799268 |
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| DOI: | 10.3390/jlpea14030044 |
