APA (7th ed.) Citation

Chauviere, B., & Stevens, K. S. (2024). Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design Exploration. Journal of Low Power Electronics & Applications, 14(3), 44. https://doi.org/10.3390/jlpea14030044

Chicago Style (17th ed.) Citation

Chauviere, Baudouin, and Kenneth S. Stevens. "Voltage Stacking: A First-Order Modelization of an M × N Asynchronous Array for Chip and Architectural Design Exploration." Journal of Low Power Electronics & Applications 14, no. 3 (2024): 44. https://doi.org/10.3390/jlpea14030044.

MLA (9th ed.) Citation

Chauviere, Baudouin, and Kenneth S. Stevens. "Voltage Stacking: A First-Order Modelization of an M × N Asynchronous Array for Chip and Architectural Design Exploration." Journal of Low Power Electronics & Applications, vol. 14, no. 3, 2024, p. 44, https://doi.org/10.3390/jlpea14030044.