APA (7th ed.) Citation

Chen, Y., Hu, Z., Zhou, X., Sun, Z., Tan, Z., & Liu, Y. (2025). P‐1.28: GOA‐AI:Designing the Size of Gate Driver on Array Circuits Using NSGA‐III(II) multi‐objective optimization algorithm framework Combined with Bayesian Optimization. SID Symposium Digest of Technical Papers, 56, 792. https://doi.org/10.1002/sdtp.18933

Chicago Style (17th ed.) Citation

Chen, Yanling, Zhenbang Hu, Xiaoliang Zhou, Zhixin Sun, Zhiwei Tan, and Yangxing Liu. "P‐1.28: GOA‐AI:Designing the Size of Gate Driver on Array Circuits Using NSGA‐III(II) Multi‐objective Optimization Algorithm Framework Combined with Bayesian Optimization." SID Symposium Digest of Technical Papers 56 (2025): 792. https://doi.org/10.1002/sdtp.18933.

MLA (9th ed.) Citation

Chen, Yanling, et al. "P‐1.28: GOA‐AI:Designing the Size of Gate Driver on Array Circuits Using NSGA‐III(II) Multi‐objective Optimization Algorithm Framework Combined with Bayesian Optimization." SID Symposium Digest of Technical Papers, vol. 56, 2025, p. 792, https://doi.org/10.1002/sdtp.18933.