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P‐1.28: GOA‐AI:Designing the Size of Gate Driver on Array Circuits Using NSGA‐III(II) multi‐objective optimization algorithm framework Combined with Bayesian Optimization.

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Title: P‐1.28: GOA‐AI:Designing the Size of Gate Driver on Array Circuits Using NSGA‐III(II) multi‐objective optimization algorithm framework Combined with Bayesian Optimization.
Authors: Chen, Yanling1, Hu, Zhenbang2, Zhou, Xiaoliang1, Sun, Zhixin1, Tan, Zhiwei1, Liu, Yangxing2
Source: SID Symposium Digest of Technical Papers; Jun2025 Supplement 1, Vol. 56, p792-796, 5p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 186835922
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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Items – Name: Title
  Label: Title
  Group: Ti
  Data: P‐1.28: GOA‐AI:Designing the Size of Gate Driver on Array Circuits Using NSGA‐III(II) multi‐objective optimization algorithm framework Combined with Bayesian Optimization.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AU" term="%22Chen%2C+Yanling%22">Chen, Yanling</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AU" term="%22Hu%2C+Zhenbang%22">Hu, Zhenbang</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AU" term="%22Zhou%2C+Xiaoliang%22">Zhou, Xiaoliang</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AU" term="%22Sun%2C+Zhixin%22">Sun, Zhixin</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AU" term="%22Tan%2C+Zhiwei%22">Tan, Zhiwei</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AU" term="%22Liu%2C+Yangxing%22">Liu, Yangxing</searchLink><relatesTo>2</relatesTo>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22SID+Symposium+Digest+of+Technical+Papers%22">SID Symposium Digest of Technical Papers</searchLink>; Jun2025 Supplement 1, Vol. 56, p792-796, 5p
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=186835922
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1002/sdtp.18933
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 5
        StartPage: 792
    Titles:
      – TitleFull: P‐1.28: GOA‐AI:Designing the Size of Gate Driver on Array Circuits Using NSGA‐III(II) multi‐objective optimization algorithm framework Combined with Bayesian Optimization.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Chen, Yanling
      – PersonEntity:
          Name:
            NameFull: Hu, Zhenbang
      – PersonEntity:
          Name:
            NameFull: Zhou, Xiaoliang
      – PersonEntity:
          Name:
            NameFull: Sun, Zhixin
      – PersonEntity:
          Name:
            NameFull: Tan, Zhiwei
      – PersonEntity:
          Name:
            NameFull: Liu, Yangxing
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 02
              M: 06
              Text: Jun2025 Supplement 1
              Type: published
              Y: 2025
          Identifiers:
            – Type: issn-print
              Value: 0097966X
          Numbering:
            – Type: volume
              Value: 56
          Titles:
            – TitleFull: SID Symposium Digest of Technical Papers
              Type: main
ResultId 1