APA (7th ed.) Citation

Perumal, V. K., Jayabalan, R., Paul, E., Selvaraj, D., & R., P. (2025). VLSI Implementation of High‐Speed and Area‐Efficient Multiplierless Address Generation Architecture for Deinterleaver in WiMAX Applications. Journal of Electrical & Computer Engineering, 2025, 1. https://doi.org/10.1155/jece/2638291

Chicago Style (17th ed.) Citation

Perumal, Vivek Karthick, Ramesh Jayabalan, Eldho Paul, Dhanasekaran Selvaraj, and Palanisamy R. "VLSI Implementation of High‐Speed and Area‐Efficient Multiplierless Address Generation Architecture for Deinterleaver in WiMAX Applications." Journal of Electrical & Computer Engineering 2025 (2025): 1. https://doi.org/10.1155/jece/2638291.

MLA (9th ed.) Citation

Perumal, Vivek Karthick, et al. "VLSI Implementation of High‐Speed and Area‐Efficient Multiplierless Address Generation Architecture for Deinterleaver in WiMAX Applications." Journal of Electrical & Computer Engineering, vol. 2025, 2025, p. 1, https://doi.org/10.1155/jece/2638291.