Optimized High Speed Design of Arithmetic BCD Block Utilizing Complementary MOS Process.
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| Title: | Optimized High Speed Design of Arithmetic BCD Block Utilizing Complementary MOS Process. |
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| Authors: | PRASAD, T. JAYACHANDRA1, CHENNAKESAVULU, M.1, chennakesavuluece@rgmcet.edu.in, REDDY, BOJJ A. RAMESH2, RAO, VADDE SEETHARAMA3, HUSSAIN, SHAIK KASHIF1 |
| Source: | Journal of Active & Passive Electronic Devices; 2025, Vol. 19 Issue 4, p283-299, 17p |
| Database: | Applied Science & Technology Source |
| ISSN: | 15550281 |
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